From patchwork Mon Mar 20 13:18:43 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ard Biesheuvel X-Patchwork-Id: 13181232 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 83AC4C76195 for ; Mon, 20 Mar 2023 13:20:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=DjfaEbgwSC51Rxb7XVoRIXLMDcLqBTv1u6A2vaIZzaw=; b=2dFii8SE5myVvp SL4a2HGVW7vE1mK2GCDiWSZHmSdPBw90/c3fHJ8jNXqMYZe9+ziBngoBCHERODH7YiYgwy89bZtpG gBmvTVcLBcWPqaKil2dMUjcYKCGIWeOG9CEmjoddUpcl2BmFkytJMDAJlmx5dZL8laIerxiXoOEk7 wq439Tz5jX9z9nWO97fva49egPd0O10NeKW/hH+zGFyRTDld7LDa+HG2DpjrArbOV0Hk9DiWAp2pH sVtM2H+U+3M/qKqo5vy/9/QwWszVBJUjOCZWRBMUuspFKW1wmM0iLzP1hi2URVA6G8nU70Gx3Xi4Q +Gk3y//rGyUSbp4GfgrA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1peFQQ-0096Gi-1L; Mon, 20 Mar 2023 13:19:46 +0000 Received: from ams.source.kernel.org ([2604:1380:4601:e00::1]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1peFPv-0095yG-2t for linux-arm-kernel@lists.infradead.org; Mon, 20 Mar 2023 13:19:17 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 885C7B80E77; Mon, 20 Mar 2023 13:19:14 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id B3DBBC433D2; Mon, 20 Mar 2023 13:19:11 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1679318353; bh=2is/UwWu7LcvlLEn4fKmvVG7CZdN8NoulubflkmBK1k=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ZqOjOpaZVFLYxNkX3JxmfrQdw1tFDsiL+Efk/oMeJN7JmJh+Xf0ALDjG/k+rs+ow5 TZVZJffl/PXhmISQvgcyReDjjHkoXRKGBkomUsQ7V//R4E4xDvwwnO34wRWXgfGTWJ szul9nZUlkqxAse7YOHXq20iCnJgf2Fxy7zZgKTZkRxowrjvgyjHLZaPOtX/FpVIcW ZZnbQKPEQ7+drFEga6GvuIk1U0fUqooQr8MKQ3gwmnyQR6Yr584ws3k8gu424i//3C Lxj1I7MHRl4DOecmeNL4x5EArGrb5vTfonJbSTFgIuo9TjTxUC9aYcfpKe/EDCXWB2 NBrVICvCQxsLA== From: Ard Biesheuvel To: linux-arm-kernel@lists.infradead.org, linux@armlinux.org.uk Cc: Ard Biesheuvel , Frederic Weisbecker , Guenter Roeck , Peter Zijlstra , Linus Walleij , Arnd Bergmann Subject: [PATCH v4 10/12] ARM: entry: Disregard Thumb undef exception in coproc dispatch Date: Mon, 20 Mar 2023 14:18:43 +0100 Message-Id: <20230320131845.3138015-11-ardb@kernel.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230320131845.3138015-1-ardb@kernel.org> References: <20230320131845.3138015-1-ardb@kernel.org> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=4564; i=ardb@kernel.org; h=from:subject; bh=2is/UwWu7LcvlLEn4fKmvVG7CZdN8NoulubflkmBK1k=; b=owGbwMvMwCFmkMcZplerG8N4Wi2JIUUi1oiTZZXNpcAQ3ntpncpp/OfOZSjIXFx+eMqM9Aq5o NaeJy87SlkYxDgYZMUUWQRm/3238/REqVrnWbIwc1iZQIYwcHEKwET0yxj+1zPJ1ThN+jt385u3 wgua3gWWP078+SVnzvejJQ+f3y2sm8Hwz/5VgXplw80ivi9dKrV3zSa6lKqtXbt5i9Z1j2MfL/w 7zQUA X-Developer-Key: i=ardb@kernel.org; a=openpgp; fpr=F43D03328115A198C90016883D200E9CA6329909 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230320_061916_226101_389B8B37 X-CRM114-Status: GOOD ( 17.64 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Now that the only remaining coprocessor instructions being handled via the dispatch in entry-armv.S are ones that only exist in a ARM (A32) encoding, we can simplify the handling of Thumb undef exceptions, and send them straight to the undefined instruction handlers in C code. Signed-off-by: Ard Biesheuvel Acked-by: Linus Walleij --- arch/arm/kernel/entry-armv.S | 64 ++++++-------------- 1 file changed, 17 insertions(+), 47 deletions(-) diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S index b4586a3447822774..0367c9581c1f05a6 100644 --- a/arch/arm/kernel/entry-armv.S +++ b/arch/arm/kernel/entry-armv.S @@ -452,12 +452,6 @@ __und_usr: @ r2 = regs->ARM_pc, which is either 2 or 4 bytes ahead of the @ faulting instruction depending on Thumb mode. @ r3 = regs->ARM_cpsr - @ - @ The emulation code returns using r9 if it has emulated the - @ instruction, or the more conventional lr if we are to treat - @ this as a real undefined instruction - @ - badr r9, ret_from_exception @ IRQs must be enabled before attempting to read the instruction from @ user space since that could cause a page/translation fault if the @@ -465,21 +459,8 @@ __und_usr: enable_irq tst r3, #PSR_T_BIT @ Thumb mode? - bne __und_usr_thumb - sub r4, r2, #4 @ ARM instr at LR - 4 -1: ldrt r0, [r4] - ARM_BE8(rev r0, r0) @ little endian instruction - - uaccess_disable ip - - @ r0 = 32-bit ARM instruction which caused the exception - @ r2 = PC value for the following instruction (:= regs->ARM_pc) - @ r4 = PC value for the faulting instruction - @ lr = 32-bit undefined instruction function - badr lr, __und_usr_fault_32 - b call_fpe + beq call_fpe -__und_usr_thumb: @ Thumb instruction sub r4, r2, #2 @ First half of thumb instr at LR - 2 #if CONFIG_ARM_THUMB && __LINUX_ARM_ARCH__ >= 6 && CONFIG_CPU_V7 @@ -501,22 +482,14 @@ __und_usr_thumb: */ .arch armv6t2 #endif -2: ldrht r5, [r4] +USERL( 4f, ldrht r5, [r4]) ARM_BE8(rev16 r5, r5) @ little endian instruction cmp r5, #0xe800 @ 32bit instruction if xx != 0 - blo __und_usr_fault_16_pan @ 16bit undefined instruction -3: ldrht r0, [r2] -ARM_BE8(rev16 r0, r0) @ little endian instruction uaccess_disable ip + blo __und_usr_fault_16 @ 16bit undefined instruction add r2, r2, #2 @ r2 is PC + 2, make it PC + 4 str r2, [sp, #S_PC] @ it's a 2x16bit instr, update - orr r0, r0, r5, lsl #16 - badr lr, __und_usr_fault_32 - @ r0 = the two 16-bit Thumb instructions which caused the exception - @ r2 = PC value for the following Thumb instruction (:= regs->ARM_pc) - @ r4 = PC value for the first 16-bit Thumb instruction - @ lr = 32bit undefined instruction function - + b __und_usr_fault_32 #if __LINUX_ARM_ARCH__ < 7 /* If the target arch was overridden, change it back: */ #ifdef CONFIG_CPU_32v6K @@ -537,14 +510,7 @@ ENDPROC(__und_usr) .pushsection .text.fixup, "ax" .align 2 4: str r4, [sp, #S_PC] @ retry current instruction - ret r9 - .popsection - .pushsection __ex_table,"a" - .long 1b, 4b -#if CONFIG_ARM_THUMB && __LINUX_ARM_ARCH__ >= 6 && CONFIG_CPU_V7 - .long 2b, 4b - .long 3b, 4b -#endif + b ret_from_exception .popsection /* @@ -558,17 +524,23 @@ ENDPROC(__und_usr) * for the ARM6/ARM7 SWI bug. * * Emulators may wish to make use of the following registers: - * r0 = instruction opcode (32-bit ARM or two 16-bit Thumb) + * r0 = instruction opcode (32-bit ARM) * r2 = PC value to resume execution after successful emulation * r9 = normal "successful" return address * r10 = this threads thread_info structure * lr = unrecognised instruction return address * IRQs enabled, FIQs enabled. */ - @ - @ Fall-through from Thumb-2 __und_usr - @ call_fpe: + badr r9, ret_from_exception + badr lr, __und_usr_fault_32 + + sub r4, r2, #4 @ ARM instr at LR - 4 +USERL( 4b, ldrt r0, [r4]) +ARM_BE8(rev r0, r0) @ little endian instruction + + uaccess_disable ip + get_thread_info r10 @ get current thread tst r0, #0x08000000 @ only CDP/CPRT/LDC/STC have bit 27 tstne r0, #0x04000000 @ bit 26 set on both ARM and Thumb-2 @@ -630,13 +602,11 @@ ENDPROC(no_fp) __und_usr_fault_32: mov r1, #4 b 1f -__und_usr_fault_16_pan: - uaccess_disable ip __und_usr_fault_16: mov r1, #2 1: mov r0, sp - badr lr, ret_from_exception - b __und_fault + bl __und_fault + b ret_from_exception ENDPROC(__und_usr_fault_32) ENDPROC(__und_usr_fault_16)