From patchwork Fri Mar 24 05:51:27 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anshuman Khandual X-Patchwork-Id: 13186459 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5EC6EC6FD20 for ; Fri, 24 Mar 2023 05:52:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-Id:Date:Subject:Cc :To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=vDMenv5U0iHK7uaOl9QmLJkvfphHrElqkR2DnbPZY0I=; b=YvpoQhv0vUX5iJ RrdE5trt7akMER0ARklLbFVbydAtK45N2bfBbWisOnLLHv2lS/H6DZmJhwA86vCoHzd+ye0K9Pv33 +Y7jz00Og/xuZ+LtSIFGlUD9XTRTWk3aVr7TaXUr38KkfvDF4bC3HG3GFhHXhmUbWNt5PCyELLKyz lOcIaOOfqrgBkCPaN6i76TOdhPDcT8AaLDD5qgpIQ7M2swL4EiZS+gbSkkPNMDF10OJJsWMI/rokx BfOj05X9VcLIbR0EvJ7JVr6+2QYeT5nYIgHR7OcyxLezCldz6skhU5B3+QU8P7OTnBIB+S9uWJARS kgt7xoEMn7JO9C1F+6kA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1pfaL4-003dLL-2e; Fri, 24 Mar 2023 05:51:46 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1pfaKz-003dJo-18 for linux-arm-kernel@lists.infradead.org; Fri, 24 Mar 2023 05:51:45 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 476A411FB; Thu, 23 Mar 2023 22:52:20 -0700 (PDT) Received: from a077893.blr.arm.com (unknown [10.162.40.17]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id E58253F766; Thu, 23 Mar 2023 22:51:33 -0700 (PDT) From: Anshuman Khandual To: linux-arm-kernel@lists.infradead.org Cc: Anshuman Khandual , Catalin Marinas , Will Deacon , Mark Brown , Marc Zyngier , linux-kernel@vger.kernel.org Subject: [PATCH] arm64: Disable EL2 traps for BRBE instructions executed in EL1 Date: Fri, 24 Mar 2023 11:21:27 +0530 Message-Id: <20230324055127.2228330-1-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230323_225141_462010_D84949E7 X-CRM114-Status: UNSURE ( 8.01 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org This disables EL2 traps for BRBE instructions executed in EL1. This would enable BRBE to be configured and used successfully in the guest kernel. Cc: Catalin Marinas Cc: Will Deacon Cc: Mark Brown Cc: Marc Zyngier Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual --- This patch applies on v6.3-rc3, after the following patch series from Mark https://lore.kernel.org/all/20230306-arm64-fgt-reg-gen-v3-0-decba93cbaab@kernel.org/ arch/arm64/include/asm/el2_setup.h | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/include/asm/el2_setup.h b/arch/arm64/include/asm/el2_setup.h index 037724b19c5c..06bf321a17be 100644 --- a/arch/arm64/include/asm/el2_setup.h +++ b/arch/arm64/include/asm/el2_setup.h @@ -161,6 +161,16 @@ msr_s SYS_HFGWTR_EL2, x0 msr_s SYS_HFGITR_EL2, xzr + mrs x1, id_aa64dfr0_el1 + ubfx x1, x1, #ID_AA64DFR0_EL1_BRBE_SHIFT, #4 + cbz x1, .Lskip_brbe_\@ + + mov x0, xzr + orr x0, x0, #HFGITR_EL2_nBRBIALL + orr x0, x0, #HFGITR_EL2_nBRBINJ + msr_s SYS_HFGITR_EL2, x0 + +.Lskip_brbe_\@: mrs x1, id_aa64pfr0_el1 // AMU traps UNDEF without AMU ubfx x1, x1, #ID_AA64PFR0_EL1_AMU_SHIFT, #4 cbz x1, .Lskip_fgt_\@