diff mbox series

[v1,2/3] KVM: arm64: Enable writable for remaining fields for ID_AA64DFR0_EL1

Message ID 20230326011950.405749-3-jingzhangos@google.com (mailing list archive)
State New, archived
Headers show
Series Enable writable for ID_AA64DFR0_EL1 and ID_DFR0_EL1 | expand

Commit Message

Jing Zhang March 26, 2023, 1:19 a.m. UTC 
Enable writable from userspace for all remaining fields in
ID_AA64DFR0_EL1, which don't need special handlings for dependency.

Signed-off-by: Jing Zhang <jingzhangos@google.com>
---
 arch/arm64/kvm/id_regs.c | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)
diff mbox series

Patch

diff --git a/arch/arm64/kvm/id_regs.c b/arch/arm64/kvm/id_regs.c
index 64691273980b..e64152aa448b 100644
--- a/arch/arm64/kvm/id_regs.c
+++ b/arch/arm64/kvm/id_regs.c
@@ -626,12 +626,32 @@  static struct id_reg_desc id_reg_descs[KVM_ARM_ID_REG_NUM] = {
 		.get_user = get_id_reg,
 		.set_user = set_id_aa64dfr0_el1, },
 	  .ftr_bits = {
+		ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE,
+			ID_AA64DFR0_EL1_DebugVer_SHIFT, ID_AA64DFR0_EL1_DebugVer_WIDTH, 0),
+		ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE,
+			ID_AA64DFR0_EL1_TraceVer_SHIFT, ID_AA64DFR0_EL1_TraceVer_WIDTH, 0),
 		ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE,
 			ID_AA64DFR0_EL1_PMUVer_SHIFT, ID_AA64DFR0_EL1_PMUVer_WIDTH, 0),
 		ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE,
 			ID_AA64DFR0_EL1_BRPs_SHIFT, ID_AA64DFR0_EL1_BRPs_WIDTH, 0),
+		ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE,
+			ID_AA64DFR0_EL1_WRPs_SHIFT, ID_AA64DFR0_EL1_WRPs_WIDTH, 0),
 		ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE,
 			ID_AA64DFR0_EL1_CTX_CMPs_SHIFT, ID_AA64DFR0_EL1_CTX_CMPs_WIDTH, 0),
+		ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE,
+			ID_AA64DFR0_EL1_PMSVer_SHIFT, ID_AA64DFR0_EL1_PMSVer_WIDTH, 0),
+		ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE,
+			ID_AA64DFR0_EL1_DoubleLock_SHIFT, ID_AA64DFR0_EL1_DoubleLock_WIDTH, 0),
+		ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE,
+			ID_AA64DFR0_EL1_TraceFilt_SHIFT, ID_AA64DFR0_EL1_TraceFilt_WIDTH, 0),
+		ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE,
+			ID_AA64DFR0_EL1_TraceBuffer_SHIFT, ID_AA64DFR0_EL1_TraceBuffer_WIDTH, 0),
+		ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE,
+			ID_AA64DFR0_EL1_MTPMU_SHIFT, ID_AA64DFR0_EL1_MTPMU_WIDTH, 0),
+		ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE,
+			ID_AA64DFR0_EL1_BRBE_SHIFT, ID_AA64DFR0_EL1_BRBE_WIDTH, 0),
+		ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE,
+			ID_AA64DFR0_EL1_HPMN0_SHIFT, ID_AA64DFR0_EL1_HPMN0_WIDTH, 0),
 		ARM64_FTR_END, },
 	  .init = init_id_aa64dfr0_el1,
 	},