From patchwork Sun Mar 26 01:19:50 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jing Zhang X-Patchwork-Id: 13187957 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 062E6C6FD1C for ; Sun, 26 Mar 2023 01:21:07 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:From:Subject:Message-ID: References:Mime-Version:In-Reply-To:Date:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=cbnerzyqqXbGi6e0yH3JzY1ORYrIQfqnCxdCsb5z+y0=; b=EdkyjVUleoXw9gnJZkP2X8BZPT BOr2JqAhthhlSvNTHXax5A9WMGyAHPU0zOfVFzLtLs8nS9v7ysX0+m7R6GK2/XHXvmsr6g0qxBgJy gNKcskfybqR3XHhzJSDl3uPmRQOFSuabYr0en4Znwa7suaXsqZ9n5T17ME9Oe/5Z3/NaTBSodjv1E pw9bUohT2x7uIerzRWWCfzECqpbgzDK4N6c2wYHQpDGmG1GkccG14RoHjJM/8zO0kq2VlSAxoD9+u /DE6rifCO4JIj8Nd/JmcQF8hlgwJkq6YsaMfp9+tFDiwVNne3dq9hs9QYHUDeIkSz6rm8Ri1qqF/t 1JjoEQ1A==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1pgF3J-007lVq-2H; Sun, 26 Mar 2023 01:20:09 +0000 Received: from mail-pl1-x649.google.com ([2607:f8b0:4864:20::649]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1pgF3A-007lTD-2G for linux-arm-kernel@lists.infradead.org; Sun, 26 Mar 2023 01:20:01 +0000 Received: by mail-pl1-x649.google.com with SMTP id u11-20020a170902e80b00b001a043e84bdfso3562106plg.23 for ; Sat, 25 Mar 2023 18:19:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; t=1679793599; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=QI/EqVJSbrviuXTqoZjivbQTyKLSha3AimdnquYMXWc=; b=XRKc51T8cnu7JDEWX9tAI7inG2D1iaT67CaXMzQVUYoEs0bP1hCXvbePNvag0nUWJ3 lUWSQDZTMvn71SCpNmYwWg6NSqpDi6KmDCloaMDl3sCsrKxH7Kb/Yr7KCiO2OTTGgHCL hJM9NipRmFgbn7WqBKNlrYDUpJV+t/fZLnZK7OfjelP2XyHlVo9O151TgkT03iSxczm0 iBAUnxoNbNJ70ax08svmq0VN5wjd8CvISdK6AQX64L5SGCx+fnI3891TxaPy1vFjD8E8 RK5FkBLxP33q2OEPScBa5fadHqDlCyMjdyRQ8S+BTWLhhSYG/QChcSrYCoUVhvLQAoc8 XgwQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1679793599; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=QI/EqVJSbrviuXTqoZjivbQTyKLSha3AimdnquYMXWc=; b=7fA1CPkzW5fpEwideArhIax215sH21pUCqYPhvuspcl9S2GwRpunZo/wZJ9+LS3yKQ ea7X+FZpFdrXiOs/W7C8I29E41VNygvfzjKf5/g2DhRbTkncS/sR8KWVu18An6qpXpK7 KqZFgjt37ZsYjkjeeDBVZpAS3osOywrGNDFI5LHI2pc8qVQDzxWKUfbWMtgmLIc3/0mV +Qn6A/QfkHow2c7Q0dr3JYkayMiHxqeHIDzS/f1uhqjMaCWd1AnD/TvyCBH5g4DKTf5z gQNpveU44YCQ96Pse+M1MEmKebWA3F9tDHCxcGBNt9nTK9LuGavVlnrfD7eoqlN2paDz 95Jg== X-Gm-Message-State: AAQBX9fdl9dGrIXeq4nyAb19tavHHn8NURFmY7RoaRaW/3HARtdgRQRm uvLCPlIquIzf+OwGWShxlFcUlninnYMvoH6Nhw== X-Google-Smtp-Source: AKy350YzdI6W2peL0PoLdiDUrbLBCuUczb8fA3S0s0TXKpTODOv4vqupPU3pSdRyK18yqYxPFmFAFTVFcG9zIn0KWA== X-Received: from jgzg.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:1acf]) (user=jingzhangos job=sendgmr) by 2002:a17:902:b94b:b0:19f:6f30:a3f6 with SMTP id h11-20020a170902b94b00b0019f6f30a3f6mr2661620pls.1.1679793599120; Sat, 25 Mar 2023 18:19:59 -0700 (PDT) Date: Sun, 26 Mar 2023 01:19:50 +0000 In-Reply-To: <20230326011950.405749-1-jingzhangos@google.com> Mime-Version: 1.0 References: <20230326011950.405749-1-jingzhangos@google.com> X-Mailer: git-send-email 2.40.0.348.gf938b09366-goog Message-ID: <20230326011950.405749-4-jingzhangos@google.com> Subject: [PATCH v1 3/3] KVM: arm64: Enable writable for all fields in ID_DFR0_EL1 From: Jing Zhang To: KVM , KVMARM , ARMLinux , Marc Zyngier , Oliver Upton Cc: Will Deacon , Paolo Bonzini , James Morse , Alexandru Elisei , Suzuki K Poulose , Fuad Tabba , Reiji Watanabe , Ricardo Koller , Raghavendra Rao Ananta , Jing Zhang X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230325_182000_736972_AAE20DCF X-CRM114-Status: UNSURE ( 8.32 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org All valid fields in ID_DFR0_EL1 are writable from usrespace with this change. Signed-off-by: Jing Zhang --- arch/arm64/kvm/id_regs.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/kvm/id_regs.c b/arch/arm64/kvm/id_regs.c index e64152aa448b..7dc2fb8121f3 100644 --- a/arch/arm64/kvm/id_regs.c +++ b/arch/arm64/kvm/id_regs.c @@ -565,8 +565,22 @@ static struct id_reg_desc id_reg_descs[KVM_ARM_ID_REG_NUM] = { .set_user = set_id_dfr0_el1, .visibility = aa32_id_visibility, }, .ftr_bits = { + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, + ID_DFR0_EL1_CopDbg_SHIFT, ID_DFR0_EL1_CopDbg_WIDTH, 0), + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, + ID_DFR0_EL1_CopSDbg_SHIFT, ID_DFR0_EL1_CopSDbg_WIDTH, 0), + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, + ID_DFR0_EL1_MMapDbg_SHIFT, ID_DFR0_EL1_MMapDbg_WIDTH, 0), + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, + ID_DFR0_EL1_CopTrc_SHIFT, ID_DFR0_EL1_CopTrc_WIDTH, 0), + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, + ID_DFR0_EL1_MMapTrc_SHIFT, ID_DFR0_EL1_MMapTrc_WIDTH, 0), + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, + ID_DFR0_EL1_MProfDbg_SHIFT, ID_DFR0_EL1_MProfDbg_WIDTH, 0), ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_PerfMon_SHIFT, ID_DFR0_EL1_PerfMon_WIDTH, 0), + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, + ID_DFR0_EL1_TraceFilt_SHIFT, ID_DFR0_EL1_TraceFilt_WIDTH, 0), ARM64_FTR_END, }, .init = init_id_dfr0_el1, },