Message ID | 20230327092103.3256118-1-s-vadapalli@ti.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
Series | [net-next] net: ethernet: ti: am65-cpsw: enable p0 host port rx_vlan_remap | expand |
Hello: This patch was applied to netdev/net-next.git (main) by Paolo Abeni <pabeni@redhat.com>: On Mon, 27 Mar 2023 14:51:03 +0530 you wrote: > From: Grygorii Strashko <grygorii.strashko@ti.com> > > By default, the tagged ingress packets to the switch from the host port > P0 get internal switch priority assigned equal to the DMA CPPI channel > number they came from, unless CPSW_P0_CONTROL_REG.RX_REMAP_VLAN is enabled. > This causes issues with applying QoS policies and mapping packets on > external port fifos, because the default configuration is vlan_aware and > DMA CPPI channels are shared between all external ports. > > [...] Here is the summary with links: - [net-next] net: ethernet: ti: am65-cpsw: enable p0 host port rx_vlan_remap https://git.kernel.org/netdev/net-next/c/86e2eca4dded You are awesome, thank you!
diff --git a/drivers/net/ethernet/ti/am65-cpsw-nuss.c b/drivers/net/ethernet/ti/am65-cpsw-nuss.c index 9ddb79776c88..907aab7dc89a 100644 --- a/drivers/net/ethernet/ti/am65-cpsw-nuss.c +++ b/drivers/net/ethernet/ti/am65-cpsw-nuss.c @@ -86,6 +86,7 @@ /* AM65_CPSW_P0_REG_CTL */ #define AM65_CPSW_P0_REG_CTL_RX_CHECKSUM_EN BIT(0) +#define AM65_CPSW_P0_REG_CTL_RX_REMAP_VLAN BIT(16) /* AM65_CPSW_PORT_REG_PRI_CTL */ #define AM65_CPSW_PORT_REG_PRI_CTL_RX_PTYPE_RROBIN BIT(8) @@ -385,8 +386,8 @@ static int am65_cpsw_nuss_common_open(struct am65_cpsw_common *common) /* set base flow_id */ writel(common->rx_flow_id_base, host_p->port_base + AM65_CPSW_PORT0_REG_FLOW_ID_OFFSET); - /* en tx crc offload */ - writel(AM65_CPSW_P0_REG_CTL_RX_CHECKSUM_EN, host_p->port_base + AM65_CPSW_P0_REG_CTL); + writel(AM65_CPSW_P0_REG_CTL_RX_CHECKSUM_EN | AM65_CPSW_P0_REG_CTL_RX_REMAP_VLAN, + host_p->port_base + AM65_CPSW_P0_REG_CTL); am65_cpsw_nuss_set_p0_ptype(common);