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[v3,1/4] ARM: dts: at91-sama5d27_wlsom1: Set sst26vf064b SPI NOR flash at its maximum frequency

Message ID 20230328101517.1595738-2-tudor.ambarus@linaro.org (mailing list archive)
State New, archived
Headers show
Series ARM: dts: at91: Set sst26vf064b SPI NOR flash at its maxumum frequency | expand

Commit Message

Tudor Ambarus March 28, 2023, 10:15 a.m. UTC 
From: Tudor Ambarus <tudor.ambarus@microchip.com>

sama5d27-wlsom1 populates an sst26vf064b SPI NOR flash. Its maximum
operating frequency for 2.7-3.6V is 104 MHz. As the flash is operated
at 3.3V, increase its maximum supported frequency to 104MHz. The
increasing of the spi-max-frequency value requires the setting of the
"CE# Not Active Hold Time", thus set the spi-cs-setup-ns to a value of 7.

The sst26vf064b datasheet specifies just a minimum value for the
"CE# Not Active Hold Time" and it advertises it to 5 ns. There's no
maximum time specified. I determined experimentally that 5 ns for the
spi-cs-setup-ns is not enough when the flash is operated close to its
maximum frequency and tests showed that 7 ns is just fine, so set the
spi-cs-setup-ns dt property to 7.

With the increase of frequency the reads are now faster with ~37%.

Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
---
 arch/arm/boot/dts/at91-sama5d27_wlsom1.dtsi | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

Comments

Tudor Ambarus March 28, 2023, 10:23 a.m. UTC | #1 
On 3/28/23 11:15, Tudor Ambarus wrote:
> From: Tudor Ambarus <tudor.ambarus@microchip.com>
> 

cut

> Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>

I don't understand why these differ. On my local machine I see them match:

commit e208a7b04cbde950588c561889d2f8eb8a10485f
Author: Tudor Ambarus <tudor.ambarus@linaro.org>
Date:   Thu Nov 17 12:52:46 2022 +0200

    ARM: dts: at91-sama5d27_wlsom1: Set sst26vf064b SPI NOR flash at its
maximum frequency

    sama5d27-wlsom1 populates an sst26vf064b SPI NOR flash. Its maximum
    operating frequency for 2.7-3.6V is 104 MHz. As the flash is operated
    at 3.3V, increase its maximum supported frequency to 104MHz. The
    increasing of the spi-max-frequency value requires the setting of the
    "CE# Not Active Hold Time", thus set the spi-cs-setup-ns to a value
of 7.

    The sst26vf064b datasheet specifies just a minimum value for the
    "CE# Not Active Hold Time" and it advertises it to 5 ns. There's no
    maximum time specified. I determined experimentally that 5 ns for the
    spi-cs-setup-ns is not enough when the flash is operated close to its
    maximum frequency and tests showed that 7 ns is just fine, so set the
    spi-cs-setup-ns dt property to 7.

    With the increase of frequency the reads are now faster with ~37%.

    Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>

Anyway, you can keep v2 then, looks like v2 has the same email on both
the author line and the S-o-b line. It's fine by me even if it is with
@microchip.com:
https://lore.kernel.org/all/20230328100723.1593864-2-tudor.ambarus@linaro.org/
diff mbox series

Patch

diff --git a/arch/arm/boot/dts/at91-sama5d27_wlsom1.dtsi b/arch/arm/boot/dts/at91-sama5d27_wlsom1.dtsi
index 83bcf9fe0152..4617805c7748 100644
--- a/arch/arm/boot/dts/at91-sama5d27_wlsom1.dtsi
+++ b/arch/arm/boot/dts/at91-sama5d27_wlsom1.dtsi
@@ -220,7 +220,8 @@  qspi1_flash: flash@0 {
 		#size-cells = <1>;
 		compatible = "jedec,spi-nor";
 		reg = <0>;
-		spi-max-frequency = <80000000>;
+		spi-max-frequency = <104000000>;
+		spi-cs-setup-ns = <7>;
 		spi-rx-bus-width = <4>;
 		spi-tx-bus-width = <4>;
 		m25p,fast-read;