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Wed, 29 Mar 2023 08:47:59 GMT Received: from hu-jinlmao-lv.qualcomm.com (10.49.16.6) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.41; Wed, 29 Mar 2023 01:47:58 -0700 From: Mao Jinlong To: Alexander Shishkin , Andy Gross , Bjorn Andersson , Konrad Dybcio , Mathieu Poirier , Suzuki K Poulose , Mike Leach , Leo Yan , Rob Herring , Krzysztof Kozlowski CC: Mao Jinlong , , , , , , Tingwei Zhang , Yuanfang Zhang , Tao Zhang , Hao Zhang Subject: [PATCH v1 7/8] coresight-tpda: Add support to configure CMB element size Date: Wed, 29 Mar 2023 01:47:43 -0700 Message-ID: <20230329084744.5705-8-quic_jinlmao@quicinc.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230329084744.5705-1-quic_jinlmao@quicinc.com> References: <20230329084744.5705-1-quic_jinlmao@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.49.16.6] X-ClientProxiedBy: nalasex01c.na.qualcomm.com (10.47.97.35) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: TsQUo688sPHWPk05tQhkPEbxFpcM8DZ_ X-Proofpoint-GUID: TsQUo688sPHWPk05tQhkPEbxFpcM8DZ_ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-03-29_02,2023-03-28_02,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 spamscore=0 clxscore=1015 adultscore=0 phishscore=0 suspectscore=0 mlxscore=0 impostorscore=0 priorityscore=1501 malwarescore=0 mlxlogscore=911 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2303200000 definitions=main-2303290071 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230329_014817_447706_9773BA6E X-CRM114-Status: GOOD ( 24.28 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Read the CMB element size from the device tree. Set the register bit that controls the CMB element size of the corresponding port. Signed-off-by: Mao Jinlong --- drivers/hwtracing/coresight/coresight-tpda.c | 33 +++++++++++++++++--- drivers/hwtracing/coresight/coresight-tpda.h | 4 +++ 2 files changed, 32 insertions(+), 5 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-tpda.c b/drivers/hwtracing/coresight/coresight-tpda.c index a620a51e861a..c2ce62e769ea 100644 --- a/drivers/hwtracing/coresight/coresight-tpda.c +++ b/drivers/hwtracing/coresight/coresight-tpda.c @@ -42,11 +42,12 @@ static int tpda_set_element_size(struct tpda_drvdata *drvdata, continue; } if (in_csdev && strstr(dev_name(&in_csdev->dev), "tpdm")) { - if (!of_property_read_u32(in_csdev->dev.parent->of_node, - "qcom,dsb-elemenet-size", &drvdata->dsb_esize[nr_inport])) - break; - dev_err(drvdata->dev, "Fail to get data set element size\n"); - return -EINVAL; + of_property_read_u32(in_csdev->dev.parent->of_node, + "qcom,dsb-elemenet-size", &drvdata->dsb_esize[nr_inport]); + of_property_read_u8(in_csdev->dev.parent->of_node, + "qcom,cmb-elemenet-size", &drvdata->cmb_esize[nr_inport]); + + break; } tpda_set_element_size(drvdata, in_csdev, 0); } @@ -82,6 +83,28 @@ static void tpda_enable_port(struct tpda_drvdata *drvdata, int port) else dev_err(drvdata->dev, "DSB data size input from port[%d] is invalid\n", port); + + /* + * Configure aggregator port n CMB data set element size + * Set the bit to 0 if the size is 8 + * Set the bit to 1 if the size is 32 + * Set the bit to 1 if the size is 64 + */ + if (drvdata->cmb_esize[port] == 8) + val &= ~TPDA_Pn_CR_CMBSIZE; + else if (drvdata->cmb_esize[port] == 32) + val |= FIELD_PREP(TPDA_Pn_CR_CMBSIZE, 0x1); + else if (drvdata->cmb_esize[port] == 32) + val |= FIELD_PREP(TPDA_Pn_CR_CMBSIZE, 0x2); + else { + /* + * CMB element size is not configured. + * Fall back to 32-bit. + */ + WARN_ON_ONCE(1); + val |= FIELD_PREP(TPDA_Pn_CR_CMBSIZE, 0x1); + } + /* Enable the port */ val |= TPDA_Pn_CR_ENA; writel_relaxed(val, drvdata->base + TPDA_Pn_CR(port)); diff --git a/drivers/hwtracing/coresight/coresight-tpda.h b/drivers/hwtracing/coresight/coresight-tpda.h index 9ec5870b5f7c..d5290d21457d 100644 --- a/drivers/hwtracing/coresight/coresight-tpda.h +++ b/drivers/hwtracing/coresight/coresight-tpda.h @@ -12,6 +12,8 @@ #define TPDA_Pn_CR_ENA BIT(0) /* Aggregator port DSB data set element size bit */ #define TPDA_Pn_CR_DSBSIZE BIT(8) +/* Aggregator port CMB data set element size bit */ +#define TPDA_Pn_CR_CMBSIZE GENMASK(7, 6) #define TPDA_MAX_INPORTS 32 @@ -26,6 +28,7 @@ * @spinlock: lock for the drvdata value. * @enable: enable status of the component. * @dsb_esize: DSB element size + * @cmb_esize: CMB element size. Must be 8, 32 or 64. */ struct tpda_drvdata { void __iomem *base; @@ -34,6 +37,7 @@ struct tpda_drvdata { spinlock_t spinlock; u8 atid; u32 dsb_esize[TPDA_MAX_INPORTS]; + u8 cmb_esize[TPDA_MAX_INPORTS]; }; #endif /* _CORESIGHT_CORESIGHT_TPDA_H */