diff mbox series

[6/6] arm64: errata: Add a commandline option to enable/disable #2701951

Message ID 20230330165128.3237939-7-james.morse@arm.com (mailing list archive)
State New, archived
Headers show
Series arm64: errata: Disable FWB on parts with non-ARM interconnects | expand

Commit Message

James Morse March 30, 2023, 4:51 p.m. UTC
Erratum #2701951 affects the FWB feature in a number of CPUs, but is
only going to be visible on parts that don't use an arm interconnect.
This is not something the operating system can discover, it has to
be described by platform firmware.

The firmware discovery API is not deployed on existing systems.

Add a commandline option to allow the workaround to override the
value from firmware, or provide a value if the firmware is not
implemented.

The property is named arm64.arm-interconnect, as this is the
description in the 'configurations affected' section of the erratum.

Signed-off-by: James Morse <james.morse@arm.com>
---
 .../admin-guide/kernel-parameters.txt         |  4 +++
 arch/arm64/kernel/cpu_errata.c                | 36 +++++++++++++++++++
 2 files changed, 40 insertions(+)
diff mbox series

Patch

diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt
index 6221a1d057dd..5898fde6a9e4 100644
--- a/Documentation/admin-guide/kernel-parameters.txt
+++ b/Documentation/admin-guide/kernel-parameters.txt
@@ -391,6 +391,10 @@ 
 	arcrimi=	[HW,NET] ARCnet - "RIM I" (entirely mem-mapped) cards
 			Format: <io>,<irq>,<nodeID>
 
+	arm64.arm-interconnect [ARM64]
+			Indicates the FWB erratum can be disabled because this
+			SoC uses an arm interconnect.
+
 	arm64.nobti	[ARM64] Unconditionally disable Branch Target
 			Identification support
 
diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c
index 55da9e588b9e..c5570904e8b4 100644
--- a/arch/arm64/kernel/cpu_errata.c
+++ b/arch/arm64/kernel/cpu_errata.c
@@ -138,6 +138,32 @@  cpu_clear_bf16_from_user_emulation(const struct arm64_cpu_capabilities *__unused
 	raw_spin_unlock(&reg_user_mask_modification);
 }
 
+static enum  {
+	FWB_WA_FORCED_ON = 1,
+	FWB_WA_UNKNOWN = 0,
+	FWB_WA_FORCED_OFF = -1,
+} __fwb_workaround_forced;
+#ifdef CONFIG_ARM64_ERRATUM_2701951
+static int __init parse_fwb_workaround_cmdline_override(char *str)
+{
+	bool arm_interconnect;
+	int ret = kstrtobool(str, &arm_interconnect);
+
+	if (ret)
+		return ret;
+
+	/*
+	 * Erratum #2701951's "Configurations Affected" says the erratum can
+	 * only be seen on SoC's "that do not use Arm interconnect IP."
+	 */
+	if (arm_interconnect)
+		__fwb_workaround_forced = FWB_WA_FORCED_OFF;
+	else
+		__fwb_workaround_forced = FWB_WA_FORCED_ON;
+	return 0;
+}
+early_param("arm64.arm-interconnect", parse_fwb_workaround_cmdline_override);
+#endif /* CONFIG_ARM64_ERRATUM_2701951 */
 bool has_stage2_fwb_errata(const struct arm64_cpu_capabilities *ignored,
 			   int scope)
 {
@@ -205,9 +231,19 @@  bool has_stage2_fwb_errata(const struct arm64_cpu_capabilities *ignored,
 		}
 
 		if (fwb_broken) {
+			if (__fwb_workaround_forced == FWB_WA_FORCED_OFF) {
+				pr_info_once("Workaround for erratum #2701951 disabled by command-line option\n");
+				return false;
+			}
 			pr_info_once("Stage-2 Force Write-Back disabled due to erratum #2701951\n");
 			return true;
 		}
+
+		/* Allow the commandline to override whatever firmware said */
+		if (has_feature && __fwb_workaround_forced == FWB_WA_FORCED_ON) {
+			pr_info_once("Workaround for erratum #2701951 enabled by command-line option\n");
+			return true;
+		}
 	}
 
 	return false;