Message ID | 20230331072058.2483975-1-peng.fan@oss.nxp.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
Series | clk: imx: imx6sx: spdif clock rate is too high for asrc | expand |
On Fri, Mar 31, 2023 at 4:15 AM Peng Fan (OSS) <peng.fan@oss.nxp.com> wrote: > > From: Shengjiu Wang <shengjiu.wang@nxp.com> > > spdif clock is one of the asrc clock source, which is used > for ideal ratio mode. when set to 98.304MHz, it cause the > divider of asrc input clock and output clock exceed the > maximum value, and asrc driver saturate the value to maximum > value, which will cause the ASRC's performance very bad. > So we need to set spdif clock to a proper rate. which make asrc > divider not exceed maximum value, at least one of divider not > exceed maximum value. > The target is spdif clock rate / output(or input) sample rate > less than 1024(which is maximum divider). Please add a Fixes tag.
diff --git a/drivers/clk/imx/clk-imx6sx.c b/drivers/clk/imx/clk-imx6sx.c index 7cf86707bc39..3face052527d 100644 --- a/drivers/clk/imx/clk-imx6sx.c +++ b/drivers/clk/imx/clk-imx6sx.c @@ -520,7 +520,7 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node) clk_set_rate(hws[IMX6SX_CLK_PLL4_AUDIO_DIV]->clk, 393216000); clk_set_parent(hws[IMX6SX_CLK_SPDIF_SEL]->clk, hws[IMX6SX_CLK_PLL4_AUDIO_DIV]->clk); - clk_set_rate(hws[IMX6SX_CLK_SPDIF_PODF]->clk, 98304000); + clk_set_rate(hws[IMX6SX_CLK_SPDIF_PODF]->clk, 24576000); clk_set_parent(hws[IMX6SX_CLK_AUDIO_SEL]->clk, hws[IMX6SX_CLK_PLL3_USB_OTG]->clk); clk_set_rate(hws[IMX6SX_CLK_AUDIO_PODF]->clk, 24000000);