| Message ID | 20230331090028.8373-5-r-gunasekaran@ti.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | arm64: j721s2: Add support for additional IPs | expand |
Hi, On 31/03/2023 12:00, Ravi Gunasekaran wrote: > From: Aswath Govindraju <a-govindraju@ti.com> > > Configure first lane to PCIe, the second lane to USB and the last two lanes > to eDP. Also, add sub-nodes to SERDES0 DT node to represent SERDES0 is > connected to PCIe. Is USB0 expected to work in super-speed on this board? If yes then you need to add USB0 lane information as well. Otherwise please ignore my comment. > > Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> > Signed-off-by: Matt Ranostay <mranostay@ti.com> > Signed-off-by: Ravi Gunasekaran <r-gunasekaran@ti.com> > --- > I had reviewed this patch in the v5 series [0]. > Since I'm taking over upstreaming this series, I removed the self > Reviewed-by tag. > > [0] - https://lore.kernel.org/all/71ce4ecd-2a50-c69d-28be-f1a8d769970e@ti.com/ > > changes from v13: > * No changes. Only rebased on top of linux-next > > Changes from v12: > * Removed enabling of "serdes_wiz" node that is already enabled in [2/8] > in this version > > Changes from v11: > * No change > > Changes from v10: > * Removed Link tag from commit message > > Changes from v9: > * Enabled serdes related nodes > > Changes from v8: > * No change > > Changes from v7: > * No change > > Changes from v6: > * No change > > Changes from v5: > * Removed Cc tags from commit message > > Changes from v4: > * No change > > Changes from v3: > * No change > > Changes from v2: > * No change > > Changes from v1: > * No change > > .../dts/ti/k3-j721s2-common-proc-board.dts | 23 +++++++++++++++++++ > 1 file changed, 23 insertions(+) > > diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts > index b4b9edfe2d12..1afefaf3f974 100644 > --- a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts > +++ b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts > @@ -9,6 +9,9 @@ > > #include "k3-j721s2-som-p0.dtsi" > #include <dt-bindings/net/ti-dp83867.h> > +#include <dt-bindings/phy/phy-cadence.h> > +#include <dt-bindings/phy/phy.h> > +#include <dt-bindings/mux/ti-serdes.h> > > / { > compatible = "ti,j721s2-evm", "ti,j721s2"; > @@ -322,6 +325,26 @@ > phy-handle = <&phy0>; > }; > > +&serdes_ln_ctrl { > + idle-states = <J721S2_SERDES0_LANE0_PCIE1_LANE0>, <J721S2_SERDES0_LANE1_USB>, > + <J721S2_SERDES0_LANE2_EDP_LANE2>, <J721S2_SERDES0_LANE3_EDP_LANE3>; > +}; > + > +&serdes_refclk { > + clock-frequency = <100000000>; > +}; > + > +&serdes0 { > + status = "okay"; > + serdes0_pcie_link: phy@0 { > + reg = <0>; > + cdns,num-lanes = <1>; > + #phy-cells = <0>; > + cdns,phy-type = <PHY_TYPE_PCIE>; > + resets = <&serdes_wiz0 1>; > + }; > +}; > + > &mcu_mcan0 { > status = "okay"; > pinctrl-names = "default"; cheers, -roger
Roger, On 25/04/23 5:15 pm, Roger Quadros wrote: > Hi, > > On 31/03/2023 12:00, Ravi Gunasekaran wrote: >> From: Aswath Govindraju <a-govindraju@ti.com> >> >> Configure first lane to PCIe, the second lane to USB and the last two lanes >> to eDP. Also, add sub-nodes to SERDES0 DT node to represent SERDES0 is >> connected to PCIe. > > Is USB0 expected to work in super-speed on this board? > If yes then you need to add USB0 lane information as well. > Otherwise please ignore my comment. > The SerDes on J721S2 can simultaneously support only two protocols. By default PCIe and DP will be supported. Due to this, USB is configured in high-speed and this does not require any SerDes lane configuration. >> >> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> >> Signed-off-by: Matt Ranostay <mranostay@ti.com> >> Signed-off-by: Ravi Gunasekaran <r-gunasekaran@ti.com> [...] > > cheers, > -roger
diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts index b4b9edfe2d12..1afefaf3f974 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts @@ -9,6 +9,9 @@ #include "k3-j721s2-som-p0.dtsi" #include <dt-bindings/net/ti-dp83867.h> +#include <dt-bindings/phy/phy-cadence.h> +#include <dt-bindings/phy/phy.h> +#include <dt-bindings/mux/ti-serdes.h> / { compatible = "ti,j721s2-evm", "ti,j721s2"; @@ -322,6 +325,26 @@ phy-handle = <&phy0>; }; +&serdes_ln_ctrl { + idle-states = <J721S2_SERDES0_LANE0_PCIE1_LANE0>, <J721S2_SERDES0_LANE1_USB>, + <J721S2_SERDES0_LANE2_EDP_LANE2>, <J721S2_SERDES0_LANE3_EDP_LANE3>; +}; + +&serdes_refclk { + clock-frequency = <100000000>; +}; + +&serdes0 { + status = "okay"; + serdes0_pcie_link: phy@0 { + reg = <0>; + cdns,num-lanes = <1>; + #phy-cells = <0>; + cdns,phy-type = <PHY_TYPE_PCIE>; + resets = <&serdes_wiz0 1>; + }; +}; + &mcu_mcan0 { status = "okay"; pinctrl-names = "default";