| Message ID | 20230403110106.983994-4-s-vadapalli@ti.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add support for J784S4 CPSW9G | expand |
On Mon, Apr 03, 2023 at 04:31:06PM +0530, Siddharth Vadapalli wrote: > TI's J784S4 SoC supports USXGMII mode. Add USXGMII mode to the > extra_modes member of the J784S4 SoC data. > > Additionally, convert the IF statement in am65_cpsw_nuss_mac_config() to > SWITCH statement to scale for new modes. Configure MAC control register > for supporting USXGMII mode and add MAC_5000FD in the "mac_capabilities" > member of struct "phylink_config". > > Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> > --- > drivers/net/ethernet/ti/am65-cpsw-nuss.c | 18 +++++++++++++++--- > 1 file changed, 15 insertions(+), 3 deletions(-) > > diff --git a/drivers/net/ethernet/ti/am65-cpsw-nuss.c b/drivers/net/ethernet/ti/am65-cpsw-nuss.c > index 6c118a9abb2f..f4d4f987563c 100644 > --- a/drivers/net/ethernet/ti/am65-cpsw-nuss.c > +++ b/drivers/net/ethernet/ti/am65-cpsw-nuss.c > @@ -1507,10 +1507,20 @@ static void am65_cpsw_nuss_mac_config(struct phylink_config *config, unsigned in > u32 mac_control = 0; > > if (common->pdata.extra_modes & BIT(state->interface)) { > - if (state->interface == PHY_INTERFACE_MODE_SGMII) { > + switch (state->interface) { > + case PHY_INTERFACE_MODE_SGMII: > mac_control |= CPSW_SL_CTL_EXT_EN; > writel(ADVERTISE_SGMII, > port->sgmii_base + AM65_CPSW_SGMII_MR_ADV_ABILITY_REG); > + break; > + > + case PHY_INTERFACE_MODE_USXGMII: > + mac_control |= CPSW_SL_CTL_XGIG | CPSW_SL_CTL_XGMII_EN; Following on to my comments on patch 1, with the addition of these control bits, you now will want am65_cpsw_nuss_mac_link_down() to avoid clearing these bits as well.
On 03/04/23 16:40, Russell King (Oracle) wrote: > On Mon, Apr 03, 2023 at 04:31:06PM +0530, Siddharth Vadapalli wrote: >> TI's J784S4 SoC supports USXGMII mode. Add USXGMII mode to the >> extra_modes member of the J784S4 SoC data. >> >> Additionally, convert the IF statement in am65_cpsw_nuss_mac_config() to >> SWITCH statement to scale for new modes. Configure MAC control register >> for supporting USXGMII mode and add MAC_5000FD in the "mac_capabilities" >> member of struct "phylink_config". >> >> Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> >> --- >> drivers/net/ethernet/ti/am65-cpsw-nuss.c | 18 +++++++++++++++--- >> 1 file changed, 15 insertions(+), 3 deletions(-) >> >> diff --git a/drivers/net/ethernet/ti/am65-cpsw-nuss.c b/drivers/net/ethernet/ti/am65-cpsw-nuss.c >> index 6c118a9abb2f..f4d4f987563c 100644 >> --- a/drivers/net/ethernet/ti/am65-cpsw-nuss.c >> +++ b/drivers/net/ethernet/ti/am65-cpsw-nuss.c >> @@ -1507,10 +1507,20 @@ static void am65_cpsw_nuss_mac_config(struct phylink_config *config, unsigned in >> u32 mac_control = 0; >> >> if (common->pdata.extra_modes & BIT(state->interface)) { >> - if (state->interface == PHY_INTERFACE_MODE_SGMII) { >> + switch (state->interface) { >> + case PHY_INTERFACE_MODE_SGMII: >> mac_control |= CPSW_SL_CTL_EXT_EN; >> writel(ADVERTISE_SGMII, >> port->sgmii_base + AM65_CPSW_SGMII_MR_ADV_ABILITY_REG); >> + break; >> + >> + case PHY_INTERFACE_MODE_USXGMII: >> + mac_control |= CPSW_SL_CTL_XGIG | CPSW_SL_CTL_XGMII_EN; > > Following on to my comments on patch 1, with the addition of these > control bits, you now will want am65_cpsw_nuss_mac_link_down() to > avoid clearing these bits as well. Yes, I will ensure this in the v3 series. Regards, Siddharth.
diff --git a/drivers/net/ethernet/ti/am65-cpsw-nuss.c b/drivers/net/ethernet/ti/am65-cpsw-nuss.c index 6c118a9abb2f..f4d4f987563c 100644 --- a/drivers/net/ethernet/ti/am65-cpsw-nuss.c +++ b/drivers/net/ethernet/ti/am65-cpsw-nuss.c @@ -1507,10 +1507,20 @@ static void am65_cpsw_nuss_mac_config(struct phylink_config *config, unsigned in u32 mac_control = 0; if (common->pdata.extra_modes & BIT(state->interface)) { - if (state->interface == PHY_INTERFACE_MODE_SGMII) { + switch (state->interface) { + case PHY_INTERFACE_MODE_SGMII: mac_control |= CPSW_SL_CTL_EXT_EN; writel(ADVERTISE_SGMII, port->sgmii_base + AM65_CPSW_SGMII_MR_ADV_ABILITY_REG); + break; + + case PHY_INTERFACE_MODE_USXGMII: + mac_control |= CPSW_SL_CTL_XGIG | CPSW_SL_CTL_XGMII_EN; + break; + + default: + /* No special configuration is required for other modes */ + break; } if (mac_control) @@ -2161,7 +2171,8 @@ am65_cpsw_nuss_init_port_ndev(struct am65_cpsw_common *common, u32 port_idx) /* Configuring Phylink */ port->slave.phylink_config.dev = &port->ndev->dev; port->slave.phylink_config.type = PHYLINK_NETDEV; - port->slave.phylink_config.mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | MAC_1000FD; + port->slave.phylink_config.mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | + MAC_1000FD | MAC_5000FD; port->slave.phylink_config.mac_managed_pm = true; /* MAC does PM */ switch (port->slave.phy_if) { @@ -2179,6 +2190,7 @@ am65_cpsw_nuss_init_port_ndev(struct am65_cpsw_common *common, u32 port_idx) case PHY_INTERFACE_MODE_QSGMII: case PHY_INTERFACE_MODE_SGMII: + case PHY_INTERFACE_MODE_USXGMII: if (common->pdata.extra_modes & BIT(port->slave.phy_if)) { __set_bit(port->slave.phy_if, port->slave.phylink_config.supported_interfaces); @@ -2804,7 +2816,7 @@ static const struct am65_cpsw_pdata j784s4_cpswxg_pdata = { .quirks = 0, .ale_dev_id = "am64-cpswxg", .fdqring_mode = K3_RINGACC_RING_MODE_MESSAGE, - .extra_modes = BIT(PHY_INTERFACE_MODE_QSGMII), + .extra_modes = BIT(PHY_INTERFACE_MODE_QSGMII) | BIT(PHY_INTERFACE_MODE_USXGMII), }; static const struct of_device_id am65_cpsw_nuss_of_mtable[] = {
TI's J784S4 SoC supports USXGMII mode. Add USXGMII mode to the extra_modes member of the J784S4 SoC data. Additionally, convert the IF statement in am65_cpsw_nuss_mac_config() to SWITCH statement to scale for new modes. Configure MAC control register for supporting USXGMII mode and add MAC_5000FD in the "mac_capabilities" member of struct "phylink_config". Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> --- drivers/net/ethernet/ti/am65-cpsw-nuss.c | 18 +++++++++++++++--- 1 file changed, 15 insertions(+), 3 deletions(-)