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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team Cc: Giuseppe Cavallaro , Alexandre Torgue , Jose Abreu , Fabio Estevam , NXP Linux Team , Maxime Coquelin , Wong Vee Khee , Kurt Kanzenbach , Mohammad Athari Bin Ismail , Andrey Konovalov , Jochen Henneberg , Tan Tee Min , Shenwei Wang , netdev@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com, imx@lists.linux.dev Subject: [PATCH v5 2/2] net: stmmac: dwmac-imx: use platform specific reset for imx93 SoCs Date: Mon, 3 Apr 2023 10:24:08 -0500 Message-Id: <20230403152408.238530-2-shenwei.wang@nxp.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230403152408.238530-1-shenwei.wang@nxp.com> References: <20230403152408.238530-1-shenwei.wang@nxp.com> X-ClientProxiedBy: BYAPR05CA0076.namprd05.prod.outlook.com (2603:10b6:a03:e0::17) To PAXPR04MB9185.eurprd04.prod.outlook.com (2603:10a6:102:231::11) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: PAXPR04MB9185:EE_|AS5PR04MB10057:EE_ X-MS-Office365-Filtering-Correlation-Id: 9489415c-8bec-4af3-74d9-08db345797a6 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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The patch implements a fix_soc_reset function and uses it specifically for the i.MX93 SoCs. Reviewed-by: Fabio Estevam Signed-off-by: Shenwei Wang --- .../net/ethernet/stmicro/stmmac/dwmac-imx.c | 27 +++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c index 2a2be65d65a0..465de3392e4e 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c @@ -37,10 +37,15 @@ #define MX93_GPR_ENET_QOS_INTF_SEL_RGMII (0x1 << 1) #define MX93_GPR_ENET_QOS_CLK_GEN_EN (0x1 << 0) +#define DMA_BUS_MODE 0x00001000 +#define DMA_BUS_MODE_SFT_RESET (0x1 << 0) +#define RMII_RESET_SPEED (0x3 << 14) + struct imx_dwmac_ops { u32 addr_width; bool mac_rgmii_txclk_auto_adj; + int (*fix_soc_reset)(void *priv, void __iomem *ioaddr); int (*set_intf_mode)(struct plat_stmmacenet_data *plat_dat); }; @@ -207,6 +212,25 @@ static void imx_dwmac_fix_speed(void *priv, unsigned int speed) dev_err(dwmac->dev, "failed to set tx rate %lu\n", rate); } +static int imx_dwmac_mx93_reset(void *priv, void __iomem *ioaddr) +{ + u32 value = readl(ioaddr + DMA_BUS_MODE); + struct plat_stmmacenet_data *plat_dat = priv; + + /* DMA SW reset */ + value |= DMA_BUS_MODE_SFT_RESET; + writel(value, ioaddr + DMA_BUS_MODE); + + if (plat_dat->interface == PHY_INTERFACE_MODE_RMII) { + usleep_range(100, 200); + writel(RMII_RESET_SPEED, ioaddr + MAC_CTRL_REG); + } + + return readl_poll_timeout(ioaddr + DMA_BUS_MODE, value, + !(value & DMA_BUS_MODE_SFT_RESET), + 10000, 1000000); +} + static int imx_dwmac_parse_dt(struct imx_priv_data *dwmac, struct device *dev) { @@ -304,6 +328,8 @@ static int imx_dwmac_probe(struct platform_device *pdev) if (ret) goto err_dwmac_init; + dwmac->plat_dat->fix_soc_reset = dwmac->ops->fix_soc_reset; + ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res); if (ret) goto err_drv_probe; @@ -337,6 +363,7 @@ static struct imx_dwmac_ops imx93_dwmac_data = { .addr_width = 32, .mac_rgmii_txclk_auto_adj = true, .set_intf_mode = imx93_set_intf_mode, + .fix_soc_reset = imx_dwmac_mx93_reset, }; static const struct of_device_id imx_dwmac_match[] = {