From patchwork Thu Apr 20 22:31:13 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 13219249 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 20D59C77B73 for ; Thu, 20 Apr 2023 22:32:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:In-Reply-To:References:Message-Id :MIME-Version:Subject:Date:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=FJOYwZl1xbvOrFrEnu9CwwGsPtSlBN1BiE+4PmzVQjY=; b=YHmI0pQU9uNMpC gviHxKEtEj/ay0Vsn6W5k82cmSyjDhALYx+BaFbCn4yQ2w/M7KIFytkY4qwUn7Xk0+upbDMd1Zv36 +S6+M2K8Jcw6fKwv6oVqhaPVQ5lhgdRntqsKqF0cOk0auilOOIlp4AxBTIqZaHSanmI5Lb5ZbNHvY vNu9/KUm1rdFQpSukCo6JJYWkehykRyaJP+bcopE3Gmm+gRHU+uJPn+atbvitoA1mRmRW2l3943gF nrBZrGGAN6v26WNMuBmgMklG2NeIL9JwcxSwtXeF71izkbxtoigb/zNJYq/HgvZdFtvuR2oO7F4UE VRbf6xvFaR5DEatPARNw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1ppcog-00984y-0A; Thu, 20 Apr 2023 22:31:50 +0000 Received: from mail-lj1-x232.google.com ([2a00:1450:4864:20::232]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1ppcoM-0097pY-10 for linux-arm-kernel@lists.infradead.org; Thu, 20 Apr 2023 22:31:32 +0000 Received: by mail-lj1-x232.google.com with SMTP id 38308e7fff4ca-2a8bca69e8bso9167471fa.3 for ; Thu, 20 Apr 2023 15:31:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1682029888; x=1684621888; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=ASYTaGq82Hkv9w/kg3EvrB+sIFVX6xhSpeewIW1eCxw=; b=nnq2DJMf11Ov8J6nqPL3xoiivBeisZSUh9KA44KiWjaVb/V8tO4ndRHSPHXMromOq8 f4qz7Go32stAqSIIk3F44rNgzKnBhrWSYILcrEQWnFQ2TCnZhU8ol2GVtb0fDkvIpfWc qtwudX3MXfTGYjt867o4YCo0XVsW161rCt00tOcz+s/STnQdgvOfhqFypmgOMEP3lf0e atK26r/PF3iG7HM5L9gU4kKVu+bVsEcDf0AGcbEpgbayJm/eb0FtnjhXZRBKTuJQojbg pOEc5JQz6lO/HtKoFlozkjkkwv8fbA4KJSfN9fQR7lbmt98LuXgOJtCujkSH44fsBZWW vgpw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1682029888; x=1684621888; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ASYTaGq82Hkv9w/kg3EvrB+sIFVX6xhSpeewIW1eCxw=; b=NNiabCJr8JF15Bz11QCaG0hHf8Her2t8vLNrzIbeQLQoxqsSwbON6DfLf3VZCBSETa upFvt/56BhcBkfMzkAa+02eGldlRiY51n07XbqPQqwnQESH7AVnLUC5Rrwp78n3eI0YJ w+PFjPdyLzX2UN+v7IUUS+DwVCqHmbOfDOsiGQyDKvBiEHgd7ZgWNI2qVRChXQ7+JOxQ 1NSIj8kZtKywP/2x/cV+zIc7NGV3T/eYnxitL5xvd4jltFFkLQ3xD06OK7UjG9NlxNKa +FSHO5hje8UBVFf/fYfF8OKPib2NZB6yJv+J3v9Ofn6XFAlQIrVVHnIX3Qwld8jo7Zqe nXLw== X-Gm-Message-State: AAQBX9fp7iGyX2p1O8ZX9PP/72b4RMeuiknds1V85jfx7DqpSsRVbdB1 7Lri7ZFuY1CLkmtAxUwRs5/VYg== X-Google-Smtp-Source: AKy350a93ndAokzSi4BUrof9fM9TLHjmTQ9rZmdw0yPnZbkwMjXJMhu+BP27ciNh5numdTrBFZ3ofA== X-Received: by 2002:a2e:721a:0:b0:2a9:f4e7:1418 with SMTP id n26-20020a2e721a000000b002a9f4e71418mr80095ljc.44.1682029888207; Thu, 20 Apr 2023 15:31:28 -0700 (PDT) Received: from [192.168.1.101] (abyj144.neoplus.adsl.tpnet.pl. [83.9.29.144]) by smtp.gmail.com with ESMTPSA id w8-20020ac25d48000000b004eedb66983csm324256lfd.273.2023.04.20.15.31.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Apr 2023 15:31:27 -0700 (PDT) From: Konrad Dybcio Date: Fri, 21 Apr 2023 00:31:13 +0200 Subject: [PATCH v2 04/13] dt-bindings: display/msm: Add SM6350 MDSS MIME-Version: 1.0 Message-Id: <20230411-topic-straitlagoon_mdss-v2-4-5def73f50980@linaro.org> References: <20230411-topic-straitlagoon_mdss-v2-0-5def73f50980@linaro.org> In-Reply-To: <20230411-topic-straitlagoon_mdss-v2-0-5def73f50980@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Krishna Manikandan , Will Deacon , Robin Murphy , Joerg Roedel Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1682029879; l=7064; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=+VotB7/AfQN9UJePv7WDKzhmnxGZ+CBYX8ro9N8OQ0o=; b=5jpT7r88RA/9BmjqBmcAEryzssmvgJGy08J1zFiDbDtlAdKrHcjd6K/wfyjeQ3cAU88MdK3/bsz1 /YvmN4C+B/4at0926ONlK0A+8Pk0P5Weze1MV6K+ZBqINSXp93mU X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230420_153130_353991_038C8ABE X-CRM114-Status: GOOD ( 12.34 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Document the SM6350 MDSS. Signed-off-by: Konrad Dybcio --- .../bindings/display/msm/qcom,sm6350-mdss.yaml | 214 +++++++++++++++++++++ 1 file changed, 214 insertions(+) diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm6350-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm6350-mdss.yaml new file mode 100644 index 000000000000..6674040d2172 --- /dev/null +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm6350-mdss.yaml @@ -0,0 +1,214 @@ +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/qcom,sm6350-mdss.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SM6350 Display MDSS + +maintainers: + - Krishna Manikandan + +description: + SM6350 MSM Mobile Display Subsystem (MDSS), which encapsulates sub-blocks + like DPU display controller, DSI and DP interfaces etc. + +$ref: /schemas/display/msm/mdss-common.yaml# + +properties: + compatible: + items: + - const: qcom,sm6350-mdss + + clocks: + items: + - description: Display AHB clock from gcc + - description: Display AXI clock from gcc + - description: Display core clock + + clock-names: + items: + - const: iface + - const: bus + - const: core + + iommus: + maxItems: 1 + + interconnects: + maxItems: 2 + + interconnect-names: + maxItems: 2 + +patternProperties: + "^display-controller@[0-9a-f]+$": + type: object + properties: + compatible: + const: qcom,sm6350-dpu + + "^dsi@[0-9a-f]+$": + type: object + properties: + compatible: + items: + - const: qcom,sm6350-dsi-ctrl + - const: qcom,mdss-dsi-ctrl + + "^phy@[0-9a-f]+$": + type: object + properties: + compatible: + const: qcom,dsi-phy-10nm + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + #include + #include + + display-subsystem@ae00000 { + compatible = "qcom,sm6350-mdss"; + reg = <0x0ae00000 0x1000>; + reg-names = "mdss"; + + power-domains = <&dispcc MDSS_GDSC>; + + clocks = <&gcc GCC_DISP_AHB_CLK>, + <&gcc GCC_DISP_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>; + clock-names = "iface", "bus", "core"; + + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + + iommus = <&apps_smmu 0x800 0x2>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + display-controller@ae01000 { + compatible = "qcom,sm6350-dpu"; + reg = <0x0ae01000 0x8f000>, + <0x0aeb0000 0x2008>; + reg-names = "mdp", "vbif"; + + clocks = <&gcc GCC_DISP_AXI_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_ROT_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names = "bus", "iface", "rot", "lut", "core", + "vsync"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>, + <&dispcc DISP_CC_MDSS_ROT_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>; + assigned-clock-rates = <300000000>, + <19200000>, + <19200000>, + <19200000>; + + interrupt-parent = <&mdss>; + interrupts = <0>; + operating-points-v2 = <&mdp_opp_table>; + power-domains = <&rpmhpd SM6350_CX>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dpu_intf1_out: endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; + + port@1 { + reg = <1>; + dpu_intf2_out: endpoint { + remote-endpoint = <&dsi1_in>; + }; + }; + }; + }; + + dsi@ae94000 { + compatible = "qcom,sm6350-dsi-ctrl", "qcom,mdss-dsi-ctrl"; + reg = <0x0ae94000 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <4>; + + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc DISP_CC_MDSS_ESC0_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_AXI_CLK>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; + assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>; + + operating-points-v2 = <&dsi_opp_table>; + power-domains = <&rpmhpd SM6350_MX>; + + phys = <&dsi0_phy>; + phy-names = "dsi"; + + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi0_in: endpoint { + remote-endpoint = <&dpu_intf1_out>; + }; + }; + + port@1 { + reg = <1>; + dsi0_out: endpoint { + }; + }; + }; + }; + + dsi0_phy: phy@ae94400 { + compatible = "qcom,dsi-phy-10nm"; + reg = <0x0ae94400 0x200>, + <0x0ae94600 0x280>, + <0x0ae94a00 0x1e0>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "ref"; + }; + }; +...