| Message ID | 20230412151831.3069211-5-fabrice.gasnier@foss.st.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | usb: dwc2: add optional clock used on stm32mp15 | expand |
diff --git a/arch/arm/boot/dts/stm32mp151.dtsi b/arch/arm/boot/dts/stm32mp151.dtsi index 4e437d3f2ed6..b71767125bf9 100644 --- a/arch/arm/boot/dts/stm32mp151.dtsi +++ b/arch/arm/boot/dts/stm32mp151.dtsi @@ -1130,8 +1130,8 @@ sdmmc3: mmc@48004000 { usbotg_hs: usb-otg@49000000 { compatible = "st,stm32mp15-hsotg", "snps,dwc2"; reg = <0x49000000 0x10000>; - clocks = <&rcc USBO_K>; - clock-names = "otg"; + clocks = <&rcc USBO_K>, <&usbphyc>; + clock-names = "otg", "utmi_clk"; resets = <&rcc USBO_R>; reset-names = "dwc2"; interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
It's needed on STM32MP15, when using the integrated full-speed PHY. This clock is an output of USBPHYC, and the HS USBPHYC is not attached as PHY in this case (managed directly by dwc2 ggpio glue): &usbotg_hs { compatible = "st,stm32mp15-fsotg", "snps,dwc2"; pinctrl-names = "default"; pinctrl-0 = <&usbotg_hs_pins_a &usbotg_fs_dp_dm_pins_a>; vbus-supply = <&vbus_otg>; status = "okay"; }; USBPHYC clock output must be used, so it can be properly enabled as a clock provider. Without this, currently, when the dualport High-Speed USBPHYC isn't requested by either USBH or OTG, it remains uninitialized when probing OTG: OTG configured with full-speed PHY isn't properly clocked, resulting in error log like: [ 2.383138] dwc2 49000000.usb-otg: dwc2_core_reset: HANG! Soft Reset timeout GRSTCTL_CSFTRST. Signed-off-by: Fabrice Gasnier <fabrice.gasnier@foss.st.com> --- arch/arm/boot/dts/stm32mp151.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)