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Thu, 13 Apr 2023 11:05:19 +0000 From: Joey Gouly To: CC: , , , , , , , , , , Subject: [PATCH v2 14/19] arm64: disable EL2 traps for PIE Date: Thu, 13 Apr 2023 12:05:08 +0100 Message-ID: <20230413110513.243326-15-joey.gouly@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230413110513.243326-1-joey.gouly@arm.com> References: <20230413110513.243326-1-joey.gouly@arm.com> MIME-Version: 1.0 X-EOPAttributedMessage: 1 X-MS-TrafficTypeDiagnostic: AM7EUR03FT045:EE_|AS8PR08MB6085:EE_|AM7EUR03FT065:EE_|GV2PR08MB8028:EE_ X-MS-Office365-Filtering-Correlation-Id: 2073911e-5d83-4642-8413-08db3c0f00a2 x-checkrecipientrouted: true NoDisclaimer: true X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0; X-Microsoft-Antispam-Message-Info-Original: w37nGv8C5ggxKjo6qT+qkCW/IVJGpvw5AeEXD10F4+4+7jB2HtqrW36dbe72VhOfR6C680oNtX2L6XPeDlzm6DEs8+9zvFzbnpNntDrP/74DO4hepuoAaFponp+sCtVVA3XgmmrznlhlLIPa93hJ2i4AGsaHNfuNhM6tpxs6gIQtJlyej0sHThOKFMgGExFYMTUNW3Y1YYMwzrJTJA58iBDeRPhwnXzIFDmnl8Z8LeSiDxZ933b2YPGCk4y4Q2kM/tU1yWHuVlhE5u5yrkPdo1+oHktD35L1YoGrM+mMufs+vKp8dG4m+oBqK6oj0iwKf5R6uO54U28NEORv64UDHaDBtxKsf8UbN1+VThGDmcoSVaHEhk8uxlyfbz0W8jJJLoEsgEJV4PHBoS/LeEyrSyuRq/0jMy/6GwMiAcVQj/SL3GXKc6/JF/NJ4p913PrLE9IfzmG0otjAUEdPY3cVn6i+QGXF7trr+puRBveyaiFDTZtpLyRoxBL6VPhFAALMbZeG2g5Hv7Yy8LXffWkSbZ3qPBusEY6/1xQHUF9iJNK9XUf9bJwtgm3Tid7A90mIOc1PzLaU6IezfrJCejCQJLcj0FipFh2AZc+i/aJmG5ixt2HX5KLBfh+ES2Xd62s4/LZwjiODRXIO6csBWz5e/+Z7jOjx43/4VftKWZcuZ0uqaxjHxlRwCzo3kFDMsVmeQo/C3JK8H5S+yZUDrE5HnQcGTBMTYHuhMl7QUpYlI90= X-Forefront-Antispam-Report-Untrusted: CIP:40.67.248.234;CTRY:IE;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:nebula.arm.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230028)(4636009)(346002)(376002)(396003)(136003)(39860400002)(451199021)(46966006)(36840700001)(40470700004)(40460700003)(82740400003)(44832011)(8936002)(5660300002)(356005)(81166007)(36860700001)(1076003)(2616005)(26005)(336012)(426003)(186003)(2906002)(47076005)(6666004)(83380400001)(478600001)(40480700001)(41300700001)(36756003)(86362001)(82310400005)(7696005)(4326008)(70206006)(70586007)(6916009)(8676002)(54906003)(19627235002)(316002)(36900700001);DIR:OUT;SFP:1101; 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X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Apr 2023 11:05:33.5258 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2073911e-5d83-4642-8413-08db3c0f00a2 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[63.35.35.123];Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: AM7EUR03FT065.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: GV2PR08MB8028 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230413_040543_890055_756F965D X-CRM114-Status: GOOD ( 10.28 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Disable trapping of TCR2_EL1 and PIRx_EL1 registers, so they can be accessed from by EL1. Signed-off-by: Joey Gouly Cc: Catalin Marinas Cc: Will Deacon Reviewed-by: Mark Brown Reviewed-by: Catalin Marinas --- arch/arm64/include/asm/el2_setup.h | 23 ++++++++++++++++++++++- 1 file changed, 22 insertions(+), 1 deletion(-) diff --git a/arch/arm64/include/asm/el2_setup.h b/arch/arm64/include/asm/el2_setup.h index 037724b19c5c..67a967647628 100644 --- a/arch/arm64/include/asm/el2_setup.h +++ b/arch/arm64/include/asm/el2_setup.h @@ -22,6 +22,17 @@ isb .endm +.macro __init_el2_hcrx + mrs x1, id_aa64mmfr1_el1 + ubfx x0, x1, #ID_AA64MMFR1_EL1_HCX_SHIFT, 4 + cbz x0, .Lskip_hcrx_\@ + + mrs_s x0, SYS_HCRX_EL2 + orr x0, x0, #HCRX_EL2_TCR2En + msr_s SYS_HCRX_EL2, x0 +.Lskip_hcrx_\@: +.endm + /* * Allow Non-secure EL1 and EL0 to access physical timer and counter. * This is not necessary for VHE, since the host kernel runs in EL2, @@ -150,12 +161,21 @@ mov x0, xzr mrs x1, id_aa64pfr1_el1 ubfx x1, x1, #ID_AA64PFR1_EL1_SME_SHIFT, #4 - cbz x1, .Lset_fgt_\@ + cbz x1, .Lset_pie_fgt_\@ /* Disable nVHE traps of TPIDR2 and SMPRI */ orr x0, x0, #HFGxTR_EL2_nSMPRI_EL1_MASK orr x0, x0, #HFGxTR_EL2_nTPIDR2_EL0_MASK +.Lset_pie_fgt_\@: + mrs_s x1, SYS_ID_AA64MMFR3_EL1 + ubfx x1, x1, #ID_AA64MMFR3_EL1_S1PIE_SHIFT, #4 + cbz x1, .Lset_fgt_\@ + + /* Disable trapping of PIR_EL1 / PIRE0_EL1 */ + orr x0, x0, #HFGxTR_EL2_nPIR_EL1 + orr x0, x0, #HFGxTR_EL2_nPIRE0_EL1 + .Lset_fgt_\@: msr_s SYS_HFGRTR_EL2, x0 msr_s SYS_HFGWTR_EL2, x0 @@ -184,6 +204,7 @@ */ .macro init_el2_state __init_el2_sctlr + __init_el2_hcrx __init_el2_timers __init_el2_debug __init_el2_lor