| Message ID | 20230420094433.42794-3-angelogioacchino.delregno@collabora.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | MT8195 Acer Tomato - devicetrees Part 3 | expand |
On Thu, Apr 20, 2023 at 5:45 PM AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> wrote: > > On Cherry boards, the IP at 0x1c015000 (dp_intf0) is used as primary > dp-intf, while the other at 0x1c113000 (dp_intf1) is used as secondary: > assign them to dp-intf{0,1} aliases respectively. > > Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> > --- > arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi | 2 ++ This should be applied at the SoC level. The display pipeline is fixed in MMSYS, so it applies to all MT8195 devices. > 1 file changed, 2 insertions(+) > > diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi > index 0820e9ba3829..918380697a9a 100644 > --- a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi > +++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi > @@ -10,6 +10,8 @@ > > / { > aliases { > + dp-intf0 = &dp_intf0; > + dp-intf1 = &dp_intf1; > i2c0 = &i2c0; > i2c1 = &i2c1; > i2c2 = &i2c2; > -- > 2.40.0 > >
Il 21/04/23 08:46, Chen-Yu Tsai ha scritto: > On Thu, Apr 20, 2023 at 5:45 PM AngeloGioacchino Del Regno > <angelogioacchino.delregno@collabora.com> wrote: >> >> On Cherry boards, the IP at 0x1c015000 (dp_intf0) is used as primary >> dp-intf, while the other at 0x1c113000 (dp_intf1) is used as secondary: >> assign them to dp-intf{0,1} aliases respectively. >> >> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> >> --- >> arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi | 2 ++ > > This should be applied at the SoC level. The display pipeline is fixed in > MMSYS, so it applies to all MT8195 devices. > It's fixed in the MMSYS configuration/driver but - as far as I remember (I can recheck on the datasheets) - the dp_intfX function can be inverted meaning that the MMSYS paths can be configured such that DP_INTF0 becomes secondary and the other becomes primary: this is why I am putting that into mt8195-cherry and not mt8195.dtsi. Regards, Angelo >> 1 file changed, 2 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi >> index 0820e9ba3829..918380697a9a 100644 >> --- a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi >> +++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi >> @@ -10,6 +10,8 @@ >> >> / { >> aliases { >> + dp-intf0 = &dp_intf0; >> + dp-intf1 = &dp_intf1; >> i2c0 = &i2c0; >> i2c1 = &i2c1; >> i2c2 = &i2c2; >> -- >> 2.40.0 >> >> >
On Mon, Apr 24, 2023 at 3:03 PM AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> wrote: > > Il 21/04/23 08:46, Chen-Yu Tsai ha scritto: > > On Thu, Apr 20, 2023 at 5:45 PM AngeloGioacchino Del Regno > > <angelogioacchino.delregno@collabora.com> wrote: > >> > >> On Cherry boards, the IP at 0x1c015000 (dp_intf0) is used as primary > >> dp-intf, while the other at 0x1c113000 (dp_intf1) is used as secondary: > >> assign them to dp-intf{0,1} aliases respectively. > >> > >> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> > >> --- > >> arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi | 2 ++ > > > > This should be applied at the SoC level. The display pipeline is fixed in > > MMSYS, so it applies to all MT8195 devices. > > > > It's fixed in the MMSYS configuration/driver but - as far as I remember (I can > recheck on the datasheets) - the dp_intfX function can be inverted meaning that > the MMSYS paths can be configured such that DP_INTF0 becomes secondary and the > other becomes primary: this is why I am putting that into mt8195-cherry and not > mt8195.dtsi. Maybe that's possible, but the diagram in the datasheet suggests a fixed path. Either way, it's not actually the problem. My original reply is probably inaccurate. AFAIK the aliases are used to identify the individual hardware blocks, which otherwise have the same compatible string. So the numbering should be the same regardless of the design and/or routing. Ideally this should be described with a proper graph though. ChenYu > > Regards, > Angelo > > >> 1 file changed, 2 insertions(+) > >> > >> diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi > >> index 0820e9ba3829..918380697a9a 100644 > >> --- a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi > >> +++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi > >> @@ -10,6 +10,8 @@ > >> > >> / { > >> aliases { > >> + dp-intf0 = &dp_intf0; > >> + dp-intf1 = &dp_intf1; > >> i2c0 = &i2c0; > >> i2c1 = &i2c1; > >> i2c2 = &i2c2; > >> -- > >> 2.40.0 > >> > >> > > >
Il 24/04/23 09:17, Chen-Yu Tsai ha scritto: > On Mon, Apr 24, 2023 at 3:03 PM AngeloGioacchino Del Regno > <angelogioacchino.delregno@collabora.com> wrote: >> >> Il 21/04/23 08:46, Chen-Yu Tsai ha scritto: >>> On Thu, Apr 20, 2023 at 5:45 PM AngeloGioacchino Del Regno >>> <angelogioacchino.delregno@collabora.com> wrote: >>>> >>>> On Cherry boards, the IP at 0x1c015000 (dp_intf0) is used as primary >>>> dp-intf, while the other at 0x1c113000 (dp_intf1) is used as secondary: >>>> assign them to dp-intf{0,1} aliases respectively. >>>> >>>> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> >>>> --- >>>> arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi | 2 ++ >>> >>> This should be applied at the SoC level. The display pipeline is fixed in >>> MMSYS, so it applies to all MT8195 devices. >>> >> >> It's fixed in the MMSYS configuration/driver but - as far as I remember (I can >> recheck on the datasheets) - the dp_intfX function can be inverted meaning that >> the MMSYS paths can be configured such that DP_INTF0 becomes secondary and the >> other becomes primary: this is why I am putting that into mt8195-cherry and not >> mt8195.dtsi. > > Maybe that's possible, but the diagram in the datasheet suggests a fixed path. > > Either way, it's not actually the problem. My original reply is probably > inaccurate. AFAIK the aliases are used to identify the individual hardware > blocks, which otherwise have the same compatible string. So the numbering > should be the same regardless of the design and/or routing. Ack. Will move to mt8195.dtsi! > > Ideally this should be described with a proper graph though. > > ChenYu > >> >> Regards, >> Angelo >> >>>> 1 file changed, 2 insertions(+) >>>> >>>> diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi >>>> index 0820e9ba3829..918380697a9a 100644 >>>> --- a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi >>>> +++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi >>>> @@ -10,6 +10,8 @@ >>>> >>>> / { >>>> aliases { >>>> + dp-intf0 = &dp_intf0; >>>> + dp-intf1 = &dp_intf1; >>>> i2c0 = &i2c0; >>>> i2c1 = &i2c1; >>>> i2c2 = &i2c2; >>>> -- >>>> 2.40.0 >>>> >>>> >>> >>
diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi index 0820e9ba3829..918380697a9a 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi @@ -10,6 +10,8 @@ / { aliases { + dp-intf0 = &dp_intf0; + dp-intf1 = &dp_intf1; i2c0 = &i2c0; i2c1 = &i2c1; i2c2 = &i2c2;
On Cherry boards, the IP at 0x1c015000 (dp_intf0) is used as primary dp-intf, while the other at 0x1c113000 (dp_intf1) is used as secondary: assign them to dp-intf{0,1} aliases respectively. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> --- arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi | 2 ++ 1 file changed, 2 insertions(+)