@@ -392,6 +392,24 @@ cpts@3d000 {
};
};
+ /* TIMERIO pad input CTRLMMR_TIMER*_CTRL registers */
+ main_timerio_input: pinctrl@104200 {
+ compatible = "pinctrl-single";
+ reg = <0x0 0x104200 0x0 0x50>;
+ #pinctrl-cells = <1>;
+ pinctrl-single,register-width = <32>;
+ pinctrl-single,function-mask = <0x000001ff>;
+ };
+
+ /* TIMERIO pad output CTCTRLMMR_TIMERIO*_CTRL registers */
+ main_timerio_output: pinctrl@104280 {
+ compatible = "pinctrl-single";
+ reg = <0x0 0x104280 0x0 0x20>;
+ #pinctrl-cells = <1>;
+ pinctrl-single,register-width = <32>;
+ pinctrl-single,function-mask = <0x0000001f>;
+ };
+
main_pmx0: pinctrl@11c000 {
compatible = "pinctrl-single";
/* Proxy 0 addressing */
@@ -173,6 +173,24 @@ chipid@43000014 {
reg = <0x00 0x43000014 0x00 0x4>;
};
+ /* MCU_TIMERIO pad input CTRLMMR_MCU_TIMER*_CTRL registers */
+ mcu_timerio_input: pinctrl@40f04200 {
+ compatible = "pinctrl-single";
+ reg = <0x0 0x40f04200 0x0 0x28>;
+ #pinctrl-cells = <1>;
+ pinctrl-single,register-width = <32>;
+ pinctrl-single,function-mask = <0x0000000F>;
+ };
+
+ /* MCU_TIMERIO pad output CTRLMMR_MCU_TIMERIO*_CTRL registers */
+ mcu_timerio_output: pinctrl@40f04280 {
+ compatible = "pinctrl-single";
+ reg = <0x0 0x40f04280 0x0 0x28>;
+ #pinctrl-cells = <1>;
+ pinctrl-single,register-width = <32>;
+ pinctrl-single,function-mask = <0x0000000F>;
+ };
+
wkup_pmx0: pinctrl@4301c000 {
compatible = "pinctrl-single";
/* Proxy 0 addressing */
There are timer IO pads in the MCU domain, and in the MAIN domain. These pads can be muxed for the related timers. There are timer IO control registers for input and output. The registers for CTRLMMR_TIMER*_CTRL and CTRLMMR_MCU_TIMER*_CTRL are used to control the input. The registers for CTCTRLMMR_TIMERIO*_CTRL and CTRLMMR_MCU_TIMERIO*_CTRL the output. The multiplexing is documented in TRM "5.1.2.3.1.4 Timer IO Muxing Control Registers" and "5.1.3.3.1.5 Timer IO Muxing Control Registers", and the CASCADE_EN bit is documented in TRM "12.6.3.1 Timers Overview". For chaining timers, the timer IO control registers also have a CASCADE_EN input bit in the CTRLMMR_TIMER*_CTRL in the registers. The CASCADE_EN bit muxes the previous timer output, or possibly and external TIMER_IO pad source, to the input clock of the selected timer instance for odd numered timers. For the even numbered timers, the CASCADE_EN bit does not do anything. The timer cascade input routing options are shown in TRM "Figure 12-3224. Timers Overview". For handling beyond multiplexing, the driver support for timer cascading should be likely be handled via the clock framework. Cc: Nishanth Menon <nm@ti.com> Cc: Vignesh Raghavendra <vigneshr@ti.com> Cc: Tony Lindgren <tony@atomide.com> Signed-off-by: Udit Kumar <u-kumar1@ti.com> --- arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 18 ++++++++++++++++++ .../arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi | 18 ++++++++++++++++++ 2 files changed, 36 insertions(+)