From patchwork Fri May 5 05:21:07 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Roman Beranek X-Patchwork-Id: 13232141 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8441CC77B7C for ; Fri, 5 May 2023 05:22:34 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=Pw760oVqxnloRW7SJoXoYq8GPZhaeldGB+SQ0VSFABM=; b=1SW/K3ymqdf74x 9gpJb9FPsoGhIkVpwmt8XzxzclXjgx9mCB8zc6qMsCj85u1Cp8SmUcrJH2RzN2jPZwti7J2OeopVg L682NoP1AyHNB38YroCoSvIVlJctDcOg0gzoJHj8cA1Pj972MCpDOkXNDeLTWUWCR7vCL/iFBCKd3 Sz07p9dft290azYx6P0fRL+MQXLip/gBhG5pbXowX0AMIqV5tRaCzDIi2baLTRZ+J2nJHUpWPjM+C nIglSAlYczeJW7w9CYAp3Z5Goh5fYu4mcdPo2RFoeM09N7smYzBknk9n+puH3ttcj3c8ao8C+NkFd UYMCVpn8IC14UNum6Pog==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1punsx-009ilV-1o; Fri, 05 May 2023 05:21:39 +0000 Received: from relay8-d.mail.gandi.net ([217.70.183.201]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1punsr-009iil-0C for linux-arm-kernel@lists.infradead.org; Fri, 05 May 2023 05:21:36 +0000 Received: (Authenticated sender: me@crly.cz) by mail.gandi.net (Postfix) with ESMTPSA id 1156A1BF206; Fri, 5 May 2023 05:21:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=crly.cz; s=gm1; t=1683264089; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=BTishZVtaZFYmhTS+E1QiU0pRfLyhtvgErYcS+oT66w=; b=GVdpRfQ/+vgBYi++UmvBh4Y77lLLjV4XQnUR02Wa1uGtdEboJRUvP2SlRJqgIndYgUV7bf A2HTns2I7UbKS8wBlemmnZEVKfAQDxFLWchJe5CBss/g2qHVcGZjEtFngnl/tApm5H8A7l fMbdVIExXmZwm74jiCf44UO/+ppvgyZWEhUYttjca9+sE05nsLhCUAX/tChhhoMZSOUlmk LoG9YlW1mwJ9vQ4thicJrxVG/+NP+VBSlzEwpgc9VNK0+58Wfufl+OGVUnyzqIysybzLW5 0ddVdLLGX5DO5ASd1DlaX3OvGdxNMjBUEteikOQ/aIIu5ZpKtgOV0NtS3LVIqQ== From: Roman Beranek To: Maxime Ripard , David Airlie , Daniel Vetter , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski Cc: Frank Oltmanns , Icenowy Zheng , Ondrej Jirman , devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 1/4] clk: sunxi-ng: a64: force select PLL_MIPI in TCON0 mux Date: Fri, 5 May 2023 07:21:07 +0200 Message-Id: <20230505052110.67514-2-me@crly.cz> X-Mailer: git-send-email 2.32.0 (Apple Git-132) In-Reply-To: <20230505052110.67514-1-me@crly.cz> References: <20230505052110.67514-1-me@crly.cz> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230504_222133_391948_BB7A141A X-CRM114-Status: GOOD ( 13.52 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org TCON0's source clock can be fed from either PLL_MIPI, or PLL_VIDEO0(2X), however MIPI DSI output only seems to work when PLL_MIPI is selected and thus the choice must be hardcoded in. Currently, this driver can't propagate rate change from N-K-M clocks (such as PLL_MIPI) upwards. This prevents PLL_VIDEO0 from participating in setting of the TCON0 data clock rate, limiting the precision with which a target pixel clock can be matched. For outputs with fixed TCON0 divider, that is DSI and LVDS, the dotclock can deviate up to 8% off target. Signed-off-by: Roman Beranek --- drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c index 41519185600a..eb36f8f77d55 100644 --- a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c +++ b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c @@ -528,11 +528,18 @@ static SUNXI_CCU_M_WITH_MUX_GATE(de_clk, "de", de_parents, 0x104, 0, 4, 24, 3, BIT(31), CLK_SET_RATE_PARENT); +/* + * DSI output seems to work only when PLL_MIPI selected. Set it and prevent + * the mux from reparenting. + */ +#define SUN50I_A64_TCON0_CLK_REG 0x118 + static const char * const tcon0_parents[] = { "pll-mipi", "pll-video0-2x" }; static const u8 tcon0_table[] = { 0, 2, }; static SUNXI_CCU_MUX_TABLE_WITH_GATE(tcon0_clk, "tcon0", tcon0_parents, tcon0_table, 0x118, 24, 3, BIT(31), - CLK_SET_RATE_PARENT); + CLK_SET_RATE_PARENT | + CLK_SET_RATE_NO_REPARENT); static const char * const tcon1_parents[] = { "pll-video0", "pll-video1" }; static const u8 tcon1_table[] = { 0, 2, }; @@ -953,6 +960,11 @@ static int sun50i_a64_ccu_probe(struct platform_device *pdev) writel(0x515, reg + SUN50I_A64_PLL_MIPI_REG); + /* Set PLL MIPI as parent for TCON0 */ + val = readl(reg + SUN50I_A64_TCON0_CLK_REG); + val &= ~GENMASK(26, 24); + writel(val | (0 << 24), reg + SUN50I_A64_TCON0_CLK_REG); + ret = devm_sunxi_ccu_probe(&pdev->dev, reg, &sun50i_a64_ccu_desc); if (ret) return ret;