From patchwork Mon May 15 17:21:35 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Davis X-Patchwork-Id: 13241868 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 80EEBC77B7D for ; Mon, 15 May 2023 17:22:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=nZajr3a/uuI5cYOphKNL6TW8yoBFuEkPZix0TfKRxjk=; b=HvLQMYagkWxwh+ U+7u2U961zG5d9SR4BeCISd/xp9nMKGSMm4uuSVxQ6ZbfU8DqwEn9H3ZALEYHXlc5yxEfatXAw3qc emkG0zaBWDD9auqGre1krV90wm/f6vp2Ui4CKL+EZe0sCYYRmODzhrvqh/sbiEoEWmOhstHbCuPc3 FRtAVBxU99V8na9Cj8WiFGLshQFrP56+sm2TK9scMH7fLGXUjWgYAWAwIZuOaZe4ubOEMaatxSffM 9i9S1JswKMLWFIpqKZpR+ERT9d80iOLXMtH4C2295uEChfcFu+eLgcBeZ5JJcBKmN6Dx+y4yf4/u6 irsWpSGEK5eIUg1iErfQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1pybtW-002vNP-2S; Mon, 15 May 2023 17:21:58 +0000 Received: from lelv0143.ext.ti.com ([198.47.23.248]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1pybtK-002vHe-0t for linux-arm-kernel@lists.infradead.org; Mon, 15 May 2023 17:21:49 +0000 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 34FHLecv021830; Mon, 15 May 2023 12:21:40 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1684171300; bh=UkMgU8qkn5zY4QqBdrumpMqK3iCsdBKO/ihSRtD5WSA=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=k1TWFnyVTzF0pTPf6Q4qOjDdwx9rJwVjs/f2OBZEnFWa0kVfExr+HuKnP1yFuvDgD kaScYTrMiAnzhGzhtfGe4O1aSvp87TrvBtDZB3uNLMpJZeKUExP1JSQAYsRqguMePe kZ26cghbXMMw6LBz+3+tcyuTDvvGmZFZdwJmEVP4= Received: from DLEE110.ent.ti.com (dlee110.ent.ti.com [157.170.170.21]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 34FHLeeo084152 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 15 May 2023 12:21:40 -0500 Received: from DLEE115.ent.ti.com (157.170.170.26) by DLEE110.ent.ti.com (157.170.170.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Mon, 15 May 2023 12:21:40 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DLEE115.ent.ti.com (157.170.170.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Mon, 15 May 2023 12:21:40 -0500 Received: from lelv0327.itg.ti.com (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 34FHLcpW002823; Mon, 15 May 2023 12:21:39 -0500 From: Andrew Davis To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Robert Nelson CC: , , , Andrew Davis Subject: [PATCH 3/5] arm64: dts: ti: k3-j721e: Enable PCIe nodes at the board level Date: Mon, 15 May 2023 12:21:35 -0500 Message-ID: <20230515172137.474626-3-afd@ti.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230515172137.474626-1-afd@ti.com> References: <20230515172137.474626-1-afd@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230515_102146_465487_5EDDC84A X-CRM114-Status: GOOD ( 13.21 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org PCIe nodes defined in the top-level J721e SoC dtsi files are incomplete and will not be functional unless they are extended with a SerDes PHY. And usually only one of the two modes can be used at a time as they share a SerDes link. As the PHY and mode is only known at the board integration level, these nodes should only be enabled when provided with this information. Disable the PCIe nodes in the dtsi files and only enable the ones that are actually pinned out on a given board. Signed-off-by: Andrew Davis --- .../boot/dts/ti/k3-j721e-beagleboneai64.dts | 16 +--------------- .../boot/dts/ti/k3-j721e-common-proc-board.dts | 7 +++---- arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 4 ++++ arch/arm64/boot/dts/ti/k3-j721e-sk.dts | 12 ++---------- 4 files changed, 10 insertions(+), 29 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts b/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts index d77eeff0d81d..be0c5431119e 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts @@ -872,12 +872,8 @@ serdes1_pcie_link: phy@0 { }; }; -&pcie0_rc { - /* Unused */ - status = "disabled"; -}; - &pcie1_rc { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&pcie1_rst_pins_default>; phys = <&serdes1_pcie_link>; @@ -887,16 +883,6 @@ &pcie1_rc { reset-gpios = <&main_gpio0 22 GPIO_ACTIVE_HIGH>; }; -&pcie2_rc { - /* Unused */ - status = "disabled"; -}; - -&pcie3_rc { - /* Unused */ - status = "disabled"; -}; - &icssg0_mdio { /* Unused */ status = "disabled"; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts index 87b7263f6547..975a5161eb96 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts @@ -820,6 +820,7 @@ &mhdp { }; &pcie0_rc { + status = "okay"; reset-gpios = <&exp1 6 GPIO_ACTIVE_HIGH>; phys = <&serdes0_pcie_link>; phy-names = "pcie-phy"; @@ -827,6 +828,7 @@ &pcie0_rc { }; &pcie1_rc { + status = "okay"; reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>; phys = <&serdes1_pcie_link>; phy-names = "pcie-phy"; @@ -834,16 +836,13 @@ &pcie1_rc { }; &pcie2_rc { + status = "okay"; reset-gpios = <&exp2 20 GPIO_ACTIVE_HIGH>; phys = <&serdes2_pcie_link>; phy-names = "pcie-phy"; num-lanes = <2>; }; -&pcie3_rc { - status = "disabled"; -}; - &icssg0_mdio { status = "disabled"; }; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi index e39f6d1e8d40..18f4661d37bf 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi @@ -814,6 +814,7 @@ pcie0_rc: pcie@2900000 { ranges = <0x01000000 0x0 0x10001000 0x0 0x10001000 0x0 0x0010000>, <0x02000000 0x0 0x10011000 0x0 0x10011000 0x0 0x7fef000>; dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; + status = "disabled"; }; pcie1_rc: pcie@2910000 { @@ -842,6 +843,7 @@ pcie1_rc: pcie@2910000 { ranges = <0x01000000 0x0 0x18001000 0x0 0x18001000 0x0 0x0010000>, <0x02000000 0x0 0x18011000 0x0 0x18011000 0x0 0x7fef000>; dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; + status = "disabled"; }; pcie2_rc: pcie@2920000 { @@ -870,6 +872,7 @@ pcie2_rc: pcie@2920000 { ranges = <0x01000000 0x0 0x00001000 0x44 0x00001000 0x0 0x0010000>, <0x02000000 0x0 0x00011000 0x44 0x00011000 0x0 0x7fef000>; dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; + status = "disabled"; }; pcie3_rc: pcie@2930000 { @@ -898,6 +901,7 @@ pcie3_rc: pcie@2930000 { ranges = <0x01000000 0x0 0x00001000 0x44 0x10001000 0x0 0x0010000>, <0x02000000 0x0 0x00011000 0x44 0x10011000 0x0 0x7fef000>; dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; + status = "disabled"; }; serdes_wiz4: wiz@5050000 { diff --git a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts index 07d3282a583b..66a8559b3755 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts @@ -872,6 +872,7 @@ serdes1_pcie_link: phy@0 { }; &pcie0_rc { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&ekey_reset_pins_default>; reset-gpios = <&main_gpio0 72 GPIO_ACTIVE_HIGH>; @@ -882,6 +883,7 @@ &pcie0_rc { }; &pcie1_rc { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&mkey_reset_pins_default>; reset-gpios = <&wkup_gpio0 11 GPIO_ACTIVE_HIGH>; @@ -891,16 +893,6 @@ &pcie1_rc { num-lanes = <2>; }; -&pcie2_rc { - /* Unused */ - status = "disabled"; -}; - -&pcie3_rc { - /* Unused */ - status = "disabled"; -}; - &icssg0_mdio { status = "disabled"; };