diff mbox series

[1/2] arm64: dts: imx8mn-beacon: Migrate sound card to simple-audio-card

Message ID 20230521231055.167351-1-aford173@gmail.com (mailing list archive)
State New, archived
Headers show
Series [1/2] arm64: dts: imx8mn-beacon: Migrate sound card to simple-audio-card | expand

Commit Message

Adam Ford May 21, 2023, 11:10 p.m. UTC 
Instead of using a custom glue layer connecting the wm8962 CODEC
to the SAI3 sound-dai, migrate the sound card to simple-audio-card.

Signed-off-by: Adam Ford <aford173@gmail.com>

Comments

Shawn Guo May 27, 2023, 12:32 p.m. UTC | #1 
On Sun, May 21, 2023 at 06:10:54PM -0500, Adam Ford wrote:
> Instead of using a custom glue layer connecting the wm8962 CODEC
> to the SAI3 sound-dai, migrate the sound card to simple-audio-card.
> 
> Signed-off-by: Adam Ford <aford173@gmail.com>

Can you double check both patches?  The changes do not seem to match
subject and commit log.

Shawn

> 
> diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
> index bd84db550053..8be8f090e8b8 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
> @@ -1069,13 +1069,6 @@ lcdif: lcdif@32e00000 {
>  					 <&clk IMX8MN_CLK_DISP_APB_ROOT>,
>  					 <&clk IMX8MN_CLK_DISP_AXI_ROOT>;
>  				clock-names = "pix", "axi", "disp_axi";
> -				assigned-clocks = <&clk IMX8MN_CLK_DISP_PIXEL_ROOT>,
> -						  <&clk IMX8MN_CLK_DISP_AXI>,
> -						  <&clk IMX8MN_CLK_DISP_APB>;
> -				assigned-clock-parents = <&clk IMX8MN_CLK_DISP_PIXEL>,
> -							 <&clk IMX8MN_SYS_PLL2_1000M>,
> -							 <&clk IMX8MN_SYS_PLL1_800M>;
> -				assigned-clock-rates = <594000000>, <500000000>, <200000000>;
>  				interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
>  				power-domains = <&disp_blk_ctrl IMX8MN_DISPBLK_PD_LCDIF>;
>  				status = "disabled";
> @@ -1093,12 +1086,6 @@ mipi_dsi: dsi@32e10000 {
>  				clocks = <&clk IMX8MN_CLK_DSI_CORE>,
>  					 <&clk IMX8MN_CLK_DSI_PHY_REF>;
>  				clock-names = "bus_clk", "sclk_mipi";
> -				assigned-clocks = <&clk IMX8MN_CLK_DSI_CORE>,
> -						  <&clk IMX8MN_CLK_DSI_PHY_REF>;
> -				assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_266M>,
> -							 <&clk IMX8MN_CLK_24M>;
> -				assigned-clock-rates = <266000000>, <24000000>;
> -				samsung,pll-clock-frequency = <24000000>;
>  				interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
>  				power-domains = <&disp_blk_ctrl IMX8MN_DISPBLK_PD_MIPI_DSI>;
>  				status = "disabled";
> @@ -1142,6 +1129,21 @@ disp_blk_ctrl: blk-ctrl@32e28000 {
>  					      "lcdif-axi", "lcdif-apb", "lcdif-pix",
>  					      "dsi-pclk", "dsi-ref",
>  					      "csi-aclk", "csi-pclk";
> +				assigned-clocks = <&clk IMX8MN_CLK_DSI_CORE>,
> +						  <&clk IMX8MN_CLK_DSI_PHY_REF>,
> +						  <&clk IMX8MN_CLK_DISP_PIXEL>,
> +						  <&clk IMX8MN_CLK_DISP_AXI>,
> +						  <&clk IMX8MN_CLK_DISP_APB>;
> +				assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_266M>,
> +							 <&clk IMX8MN_CLK_24M>,
> +							 <&clk IMX8MN_VIDEO_PLL1_OUT>,
> +							 <&clk IMX8MN_SYS_PLL2_1000M>,
> +							 <&clk IMX8MN_SYS_PLL1_800M>;
> +				assigned-clock-rates = <266000000>,
> +						       <24000000>,
> +						       <594000000>,
> +						       <500000000>,
> +						       <200000000>;
>  				#power-domain-cells = <1>;
>  			};
>  
> -- 
> 2.39.2
>
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
index bd84db550053..8be8f090e8b8 100644
--- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
@@ -1069,13 +1069,6 @@  lcdif: lcdif@32e00000 {
 					 <&clk IMX8MN_CLK_DISP_APB_ROOT>,
 					 <&clk IMX8MN_CLK_DISP_AXI_ROOT>;
 				clock-names = "pix", "axi", "disp_axi";
-				assigned-clocks = <&clk IMX8MN_CLK_DISP_PIXEL_ROOT>,
-						  <&clk IMX8MN_CLK_DISP_AXI>,
-						  <&clk IMX8MN_CLK_DISP_APB>;
-				assigned-clock-parents = <&clk IMX8MN_CLK_DISP_PIXEL>,
-							 <&clk IMX8MN_SYS_PLL2_1000M>,
-							 <&clk IMX8MN_SYS_PLL1_800M>;
-				assigned-clock-rates = <594000000>, <500000000>, <200000000>;
 				interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
 				power-domains = <&disp_blk_ctrl IMX8MN_DISPBLK_PD_LCDIF>;
 				status = "disabled";
@@ -1093,12 +1086,6 @@  mipi_dsi: dsi@32e10000 {
 				clocks = <&clk IMX8MN_CLK_DSI_CORE>,
 					 <&clk IMX8MN_CLK_DSI_PHY_REF>;
 				clock-names = "bus_clk", "sclk_mipi";
-				assigned-clocks = <&clk IMX8MN_CLK_DSI_CORE>,
-						  <&clk IMX8MN_CLK_DSI_PHY_REF>;
-				assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_266M>,
-							 <&clk IMX8MN_CLK_24M>;
-				assigned-clock-rates = <266000000>, <24000000>;
-				samsung,pll-clock-frequency = <24000000>;
 				interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
 				power-domains = <&disp_blk_ctrl IMX8MN_DISPBLK_PD_MIPI_DSI>;
 				status = "disabled";
@@ -1142,6 +1129,21 @@  disp_blk_ctrl: blk-ctrl@32e28000 {
 					      "lcdif-axi", "lcdif-apb", "lcdif-pix",
 					      "dsi-pclk", "dsi-ref",
 					      "csi-aclk", "csi-pclk";
+				assigned-clocks = <&clk IMX8MN_CLK_DSI_CORE>,
+						  <&clk IMX8MN_CLK_DSI_PHY_REF>,
+						  <&clk IMX8MN_CLK_DISP_PIXEL>,
+						  <&clk IMX8MN_CLK_DISP_AXI>,
+						  <&clk IMX8MN_CLK_DISP_APB>;
+				assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_266M>,
+							 <&clk IMX8MN_CLK_24M>,
+							 <&clk IMX8MN_VIDEO_PLL1_OUT>,
+							 <&clk IMX8MN_SYS_PLL2_1000M>,
+							 <&clk IMX8MN_SYS_PLL1_800M>;
+				assigned-clock-rates = <266000000>,
+						       <24000000>,
+						       <594000000>,
+						       <500000000>,
+						       <200000000>;
 				#power-domain-cells = <1>;
 			};