| Message ID | 20230522093002.75137-3-angelogioacchino.delregno@collabora.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | MT8192/95: Set correct MSDCPLL rate | expand |
diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index a44aae4ab953..daac8e050ce7 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -852,6 +852,8 @@ apmixedsys: syscon@1000c000 { compatible = "mediatek,mt8195-apmixedsys", "syscon"; reg = <0 0x1000c000 0 0x1000>; #clock-cells = <1>; + assigned-clocks = <&apmixedsys CLK_APMIXED_MSDCPLL>; + assigned-clock-rates = <400000000>; }; systimer: timer@10017000 {
Some bootloaders will set MSDCPLL's rate lower than 400MHz: what I have seen is this clock being set at around 384MHz. This is a performance concern (and possibly a stability one, for picky eMMC/SD cards) as the MSDC controller's internal divier will choose a frequency that is lower than expected, in the end causing a difference in the expected mmc/sd device's timings. Make sure that the MSDCPLL frequency is always set to 400MHz to both improve performance and reliability of the sd/mmc storage. Fixes: 37f2582883be ("arm64: dts: Add mediatek SoC mt8195 and evaluation board") Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 2 ++ 1 file changed, 2 insertions(+)