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Fri, 26 May 2023 15:35:42 GMT Received: from jinlmao-gv.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.42; Fri, 26 May 2023 08:35:38 -0700 From: Mao Jinlong To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Suzuki K Poulose , Mike Leach , Leo Yan , Rob Herring , Krzysztof Kozlowski CC: Mao Jinlong , , , , , , Tingwei Zhang , Yuanfang Zhang , "Tao Zhang" , Hao Zhang Subject: [PATCH v1 3/3] dt-bindings: arm: Adds CoreSight CSR hardware definitions Date: Fri, 26 May 2023 23:35:08 +0800 Message-ID: <20230526153508.6208-4-quic_jinlmao@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230526153508.6208-1-quic_jinlmao@quicinc.com> References: <20230526153508.6208-1-quic_jinlmao@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: _F45BSa2RxZyMLkuekuQimFzCumjr_nn X-Proofpoint-ORIG-GUID: _F45BSa2RxZyMLkuekuQimFzCumjr_nn X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.573,FMLib:17.11.176.26 definitions=2023-05-26_06,2023-05-25_03,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 phishscore=0 suspectscore=0 clxscore=1015 adultscore=0 bulkscore=0 malwarescore=0 priorityscore=1501 impostorscore=0 lowpriorityscore=0 spamscore=0 mlxlogscore=999 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2304280000 definitions=main-2305260131 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230526_083547_930902_94EF2135 X-CRM114-Status: GOOD ( 17.71 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Adds new coresight-csr.yaml file describing the bindings required to define csr in the device trees. Signed-off-by: Mao Jinlong --- .../bindings/arm/qcom,coresight-csr.yaml | 62 +++++++++++++++++++ 1 file changed, 62 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/qcom,coresight-csr.yaml diff --git a/Documentation/devicetree/bindings/arm/qcom,coresight-csr.yaml b/Documentation/devicetree/bindings/arm/qcom,coresight-csr.yaml new file mode 100644 index 000000000000..a79b4f6a8bdf --- /dev/null +++ b/Documentation/devicetree/bindings/arm/qcom,coresight-csr.yaml @@ -0,0 +1,62 @@ +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +# Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/qcom,coresight-csr.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: CoreSight Slave Register - TPDA + +description: | + CoreSight Slave Register block hosts miscellaneous configuration registers. + Those configuration registers can be used to control, various coresight + configurations. + +maintainers: + - Mao Jinlong + - Hao Zhang + +properties: + $nodename: + pattern: "^csr(@[0-9a-f]+)$" + compatible: + items: + - const: qcom,coresight-csr + + reg: + minItems: 1 + maxItems: 2 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: apb_pclk + + qcom,set-byte-cntr-support: + $ref: /schemas/types.yaml#/definitions/flag + description: + If set, indicates that CSR supports to set ETR_IRQ_CTRL register. + +required: + - compatible + - reg + - clocks + - clock-names + +additionalProperties: false + +examples: + # minimum CSR definition. + - | + csr@10001000 { + compatible = "qcom,coresight-csr"; + reg = <0 0x10001000 0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + qcom,set-byte-cntr-support; + }; + +...