From patchwork Fri Jun 2 08:23:24 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sricharan Ramabadhran X-Patchwork-Id: 13264859 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 53539C7EE2A for ; Fri, 2 Jun 2023 08:25:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:To:From:Reply-To:Cc:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=hmMj0HPwNPsxNhFA5K1W+152wPYkOah7+31GiAG5uWc=; b=YiuJCXZjyTfBa2 m9mG8gZ0HLu8prAwuX6mG7H0GA/s3ym8z6/7x9qxf5FVOk2gTMAt4ojqIGtxmGpErK0g66b1xBfoI XuBKF0A4+8Dp5L6eNW3oXcSpeuBlejFYVjRIXMW2zZsE3Zr/nMTKK9jpOFxUlmNfQGOz+2hBbisTh HUPFh6EhDdST27J0+nfsziXJYra/ja68wTebeAEvBcAsrlItKNje3MsIKwcV5RkG0ICBmNLvUkgkj jXRyOKxrXVrFolUYKgrZkdcQ1CuN2roozBafUjZ5zob6mB3RLS3ycL/06l7cZQDAIQU1ZjllMHGtr lDXilq9N+qbIgIdjpZjQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1q506A-0068fC-2Y; Fri, 02 Jun 2023 08:25:26 +0000 Received: from mx0a-0031df01.pphosted.com ([205.220.168.131]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1q5067-0068dM-29 for linux-arm-kernel@lists.infradead.org; Fri, 02 Jun 2023 08:25:25 +0000 Received: from pps.filterd (m0279866.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 3527uHIl028597; Fri, 2 Jun 2023 08:25:16 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=qcppdkim1; bh=Z6RNy81swJVhMHqvoJAfHakZB1syZn96spNjZp2ajc0=; b=U7QuJT9bTYPGA1Mp+al26Pn/yYXCBE59IVo+nf/h0+Mex/pEVokmZ7lrYG0NDEoioSpc vmjg6AwlOipBJ6hxQ8e/BdMVQjQGGCfou9LyKvYEjED2JthbHOYHLqu3SRwWZTV9soGL Mtr73t4nLHD1/7SSsOrgSfUnlsdJjDmlfQqrObI6ps02em4SOTMvPN/NIAV7b57qqqkD Gx7pLNx/DFSUk125zOUKXY4IkWCGZ5kE11AkGa61TH+nbcSiRHx56SoA9cPGzCVob0ek rOZVJihlVeU14mLr+VieHXe8yJavUznFG/nISN/ZsB24IQEX3bMVoPOHXQwmNbfa0j4r Gw== Received: from nalasppmta02.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3qy1bch5d6-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 02 Jun 2023 08:25:16 +0000 Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA02.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3528PFGi005129 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 2 Jun 2023 08:25:15 GMT Received: from win-platform-upstream01.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.42; Fri, 2 Jun 2023 01:25:08 -0700 From: Sricharan Ramabadhran To: , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH V8 7/8] arm64: dts: Add ipq5018 SoC and rdp432-c2 board support Date: Fri, 2 Jun 2023 13:53:24 +0530 Message-ID: <20230602082325.1445261-8-quic_srichara@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230602082325.1445261-1-quic_srichara@quicinc.com> References: <20230602082325.1445261-1-quic_srichara@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: Z3IcvB-Iyznnihj4j0N6H2Lir5XaOrS5 X-Proofpoint-GUID: Z3IcvB-Iyznnihj4j0N6H2Lir5XaOrS5 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.573,FMLib:17.11.176.26 definitions=2023-06-02_05,2023-05-31_03,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 spamscore=0 malwarescore=0 bulkscore=0 mlxscore=0 lowpriorityscore=0 suspectscore=0 mlxlogscore=999 adultscore=0 clxscore=1015 priorityscore=1501 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2304280000 definitions=main-2306020064 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230602_012523_711894_BBCA2270 X-CRM114-Status: GOOD ( 21.92 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add initial device tree support for the Qualcomm IPQ5018 SoC and rdp432-c2 board. Few things like 'reboot' does not work because, couple of more 'SCM' APIS are needed to clear some TrustZone settings. Those will be posted separately. Reviewed-by: Krzysztof Kozlowski Co-developed-by: Varadarajan Narayanan Signed-off-by: Varadarajan Narayanan Co-developed-by: Gokul Sriram Palanisamy Signed-off-by: Gokul Sriram Palanisamy Signed-off-by: Sricharan Ramabadhran --- arch/arm64/boot/dts/qcom/Makefile | 1 + .../arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts | 72 +++++ arch/arm64/boot/dts/qcom/ipq5018.dtsi | 250 ++++++++++++++++++ 3 files changed, 323 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts create mode 100644 arch/arm64/boot/dts/qcom/ipq5018.dtsi diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 4f9e81253e18..a2572f4a3729 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -4,6 +4,7 @@ dtb-$(CONFIG_ARCH_QCOM) += apq8039-t2.dtb dtb-$(CONFIG_ARCH_QCOM) += apq8094-sony-xperia-kitakami-karin_windy.dtb dtb-$(CONFIG_ARCH_QCOM) += apq8096-db820c.dtb dtb-$(CONFIG_ARCH_QCOM) += apq8096-ifc6640.dtb +dtb-$(CONFIG_ARCH_QCOM) += ipq5018-rdp432-c2.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq5332-mi01.2.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq5332-rdp442.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq5332-rdp468.dtb diff --git a/arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts b/arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts new file mode 100644 index 000000000000..e636a1cb9b77 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts @@ -0,0 +1,72 @@ +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +/* + * IPQ5018 MP03.1-C2 board device tree source + * + * Copyright (c) 2023 The Linux Foundation. All rights reserved. + */ + +/dts-v1/; + +#include "ipq5018.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. IPQ5018/AP-RDP432.1-C2"; + compatible = "qcom,ipq5018-rdp432-c2", "qcom,ipq5018"; + + aliases { + serial0 = &blsp1_uart1; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&blsp1_uart1 { + pinctrl-0 = <&uart1_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&sdhc_1 { + pinctrl-0 = <&sdc_default_state>; + pinctrl-names = "default"; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + max-frequency = <192000000>; + bus-width = <4>; + status = "okay"; +}; + +&sleep_clk { + clock-frequency = <32000>; +}; + +&tlmm { + sdc_default_state: sdc-default-state { + clk-pins { + pins = "gpio9"; + function = "sdc1_clk"; + drive-strength = <8>; + bias-disable; + }; + + cmd-pins { + pins = "gpio8"; + function = "sdc1_cmd"; + drive-strength = <8>; + bias-pull-up; + }; + + data-pins { + pins = "gpio4", "gpio5", "gpio6", "gpio7"; + function = "sdc1_data"; + drive-strength = <8>; + bias-disable; + }; + }; +}; + +&xo_board_clk { + clock-frequency = <24000000>; +}; diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qcom/ipq5018.dtsi new file mode 100644 index 000000000000..9f13d2dcdfd5 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi @@ -0,0 +1,250 @@ +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +/* + * IPQ5018 SoC device tree source + * + * Copyright (c) 2023 The Linux Foundation. All rights reserved. + */ + +#include +#include +#include + +/ { + interrupt-parent = <&intc>; + #address-cells = <2>; + #size-cells = <2>; + + clocks { + sleep_clk: sleep-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; + + xo_board_clk: xo-board-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + }; + + CPU1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x1>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + }; + + L2_0: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-size = <0x80000>; + cache-unified; + }; + }; + + firmware { + scm { + compatible = "qcom,scm-ipq5018", "qcom,scm"; + }; + }; + + memory@40000000 { + device_type = "memory"; + /* We expect the bootloader to fill in the size */ + reg = <0x0 0x40000000 0x0 0x0>; + }; + + pmu { + compatible = "arm,cortex-a53-pmu"; + interrupts = ; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + tz_region: tz@4ac00000 { + reg = <0x0 0x4ac00000 0x0 0x200000>; + no-map; + }; + }; + + soc: soc@0 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0 0xffffffff>; + + tlmm: pinctrl@1000000 { + compatible = "qcom,ipq5018-tlmm"; + reg = <0x01000000 0x300000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&tlmm 0 0 47>; + interrupt-controller; + #interrupt-cells = <2>; + + uart1_pins: uart1-state { + pins = "gpio31", "gpio32", "gpio33", "gpio34"; + function = "blsp1_uart1"; + drive-strength = <8>; + bias-pull-down; + }; + }; + + gcc: clock-controller@1800000 { + compatible = "qcom,gcc-ipq5018"; + reg = <0x01800000 0x80000>; + clocks = <&xo_board_clk>, + <&sleep_clk>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + + sdhc_1: mmc@7804000 { + compatible = "qcom,ipq5018-sdhci", "qcom,sdhci-msm-v5"; + reg = <0x7804000 0x1000>; + reg-names = "hc"; + + interrupts = , + ; + interrupt-names = "hc_irq", "pwr_irq"; + + clocks = <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_APPS_CLK>, + <&xo_board_clk>; + clock-names = "iface", "core", "xo"; + non-removable; + status = "disabled"; + }; + + blsp1_uart1: serial@78af000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0x078af000 0x200>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + }; + + intc: interrupt-controller@b000000 { + compatible = "qcom,msm-qgic2"; + reg = <0x0b000000 0x1000>, /* GICD */ + <0x0b002000 0x2000>, /* GICC */ + <0x0b001000 0x1000>, /* GICH */ + <0x0b004000 0x2000>; /* GICV */ + interrupts = ; + interrupt-controller; + #interrupt-cells = <3>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x0b00a000 0x1ffa>; + + v2m0: v2m@0 { + compatible = "arm,gic-v2m-frame"; + reg = <0x00000000 0xff8>; + msi-controller; + }; + + v2m1: v2m@1000 { + compatible = "arm,gic-v2m-frame"; + reg = <0x00001000 0xff8>; + msi-controller; + }; + }; + + timer@b120000 { + compatible = "arm,armv7-timer-mem"; + reg = <0x0b120000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + frame@b120000 { + reg = <0x0b121000 0x1000>, + <0x0b122000 0x1000>; + interrupts = , + ; + frame-number = <0>; + }; + + frame@b123000 { + reg = <0xb123000 0x1000>; + interrupts = ; + frame-number = <1>; + status = "disabled"; + }; + + frame@b124000 { + frame-number = <2>; + interrupts = ; + reg = <0x0b124000 0x1000>; + status = "disabled"; + }; + + frame@b125000 { + reg = <0x0b125000 0x1000>; + interrupts = ; + frame-number = <3>; + status = "disabled"; + }; + + frame@b126000 { + reg = <0x0b126000 0x1000>; + interrupts = ; + frame-number = <4>; + status = "disabled"; + }; + + frame@b127000 { + reg = <0x0b127000 0x1000>; + interrupts = ; + frame-number = <5>; + status = "disabled"; + }; + + frame@b128000 { + reg = <0x0b128000 0x1000>; + interrupts = ; + frame-number = <6>; + status = "disabled"; + }; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; +};