| Message ID | 20230605133031.1827626-1-suzuki.poulose@arm.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | coresight: etm4x: Match all ETM4 instances based on DEVARCH and DEVTYPE | expand |
On Mon, 5 Jun 2023 at 14:30, Suzuki K Poulose <suzuki.poulose@arm.com> wrote: > > Instead of adding the PIDs forever to the list for the new CPUs, let us detect > a component to be ETMv4 based on the CoreSight CID, DEVTYPE=PE_TRACE and > DEVARCH=ETMv4. This is already done for some of the ETMs. We can extend the PID > matching to match the PIDR2:JEDEC, BIT[3], which must be 1 (RA0) always. > > Link: https://lkml.kernel.org/r/20230317030501.1811905-1-anshuman.khandual@arm.com > Cc: Anshuman Khandual <anshuman.khandual@arm.com> > Cc: Rob Herring <robh+dt@kernel.org> > Cc: frowand.list@gmail.com > Cc: linux@armlinux.org.uk > Cc: Mike Leach <mike.leach@linaro.org> > Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> > --- > .../coresight/coresight-etm4x-core.c | 5 +++++ > drivers/hwtracing/coresight/coresight-priv.h | 19 +++++++++++++++++-- > 2 files changed, 22 insertions(+), 2 deletions(-) > > diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c > index 4c15fae534f3..8a2e24d5686a 100644 > --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c > +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c > @@ -2260,6 +2260,11 @@ static const struct amba_id etm4_ids[] = { > CS_AMBA_UCI_ID(0x000cc0af, uci_id_etm4),/* Marvell ThunderX2 */ > CS_AMBA_UCI_ID(0x000b6d01, uci_id_etm4),/* HiSilicon-Hip08 */ > CS_AMBA_UCI_ID(0x000b6d02, uci_id_etm4),/* HiSilicon-Hip09 */ > + /* > + * Match all PIDs with ETM4 DEVARCH. No need for adding any of the new > + * CPUs to the list here. > + */ > + CS_AMBA_MATCH_ALL_UCI(uci_id_etm4), > {}, > }; > > diff --git a/drivers/hwtracing/coresight/coresight-priv.h b/drivers/hwtracing/coresight/coresight-priv.h > index 595ce5862056..72ec36c9232c 100644 > --- a/drivers/hwtracing/coresight/coresight-priv.h > +++ b/drivers/hwtracing/coresight/coresight-priv.h > @@ -193,12 +193,27 @@ extern void coresight_remove_cti_ops(void); > } > > /* coresight AMBA ID, full UCI structure: id table entry. */ > -#define CS_AMBA_UCI_ID(pid, uci_ptr) \ > +#define __CS_AMBA_UCI_ID(pid, m, uci_ptr) \ > { \ > .id = pid, \ > - .mask = 0x000fffff, \ > + .mask = m, \ > .data = (void *)uci_ptr \ > } > +#define CS_AMBA_UCI_ID(pid, uci) __CS_AMBA_UCI_ID(pid, 0x000fffff, uci) > +/* > + * PIDR2[JEDEC], BIT(3) must be 1 (Read As One) to indicate that rest of the > + * PIDR1, PIDR2 DES_* fields follow JEDEC encoding for the designer. Use that > + * as a match value for blanket matching all devices in the given CoreSight > + * device type and architecture. > + */ > +#define PIDR2_JEDEC BIT(3) > +#define PID_PIDR2_JEDEC (PIDR2_JEDEC << 16) > +/* > + * Match all PIDs in a given CoreSight device type and architecture, defined > + * by the uci. > + */ > +#define CS_AMBA_MATCH_ALL_UCI(uci) \ > + __CS_AMBA_UCI_ID(PID_PIDR2_JEDEC, PID_PIDR2_JEDEC, uci) > > /* extract the data value from a UCI structure given amba_id pointer. */ > static inline void *coresight_get_uci_data(const struct amba_id *id) > -- > 2.34.1 > Reviewed by:- Mike Leach <mike.leach@linaro.org>
On 07/06/2023 11:43, Mike Leach wrote: > On Mon, 5 Jun 2023 at 14:30, Suzuki K Poulose <suzuki.poulose@arm.com> wrote: >> >> Instead of adding the PIDs forever to the list for the new CPUs, let us detect >> a component to be ETMv4 based on the CoreSight CID, DEVTYPE=PE_TRACE and >> DEVARCH=ETMv4. This is already done for some of the ETMs. We can extend the PID >> matching to match the PIDR2:JEDEC, BIT[3], which must be 1 (RA0) always. Fix RA0 => RAO >> >> Link: https://lkml.kernel.org/r/20230317030501.1811905-1-anshuman.khandual@arm.com >> Cc: Anshuman Khandual <anshuman.khandual@arm.com> >> Cc: Rob Herring <robh+dt@kernel.org> >> Cc: frowand.list@gmail.com >> Cc: linux@armlinux.org.uk >> Cc: Mike Leach <mike.leach@linaro.org> >> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> >> +#define PIDR2_JEDEC BIT(3) >> +#define PID_PIDR2_JEDEC (PIDR2_JEDEC << 16) >> +/* >> + * Match all PIDs in a given CoreSight device type and architecture, defined >> + * by the uci. >> + */ >> +#define CS_AMBA_MATCH_ALL_UCI(uci) \ >> + __CS_AMBA_UCI_ID(PID_PIDR2_JEDEC, PID_PIDR2_JEDEC, uci) >> >> /* extract the data value from a UCI structure given amba_id pointer. */ >> static inline void *coresight_get_uci_data(const struct amba_id *id) >> -- >> 2.34.1 >> > Reviewed by:- Mike Leach <mike.leach@linaro.org> > Thanks Mike, I have queued this, with the above fix: [01] https://git.kernel.org/coresight/c/ab5ca6268afc
diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c index 4c15fae534f3..8a2e24d5686a 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -2260,6 +2260,11 @@ static const struct amba_id etm4_ids[] = { CS_AMBA_UCI_ID(0x000cc0af, uci_id_etm4),/* Marvell ThunderX2 */ CS_AMBA_UCI_ID(0x000b6d01, uci_id_etm4),/* HiSilicon-Hip08 */ CS_AMBA_UCI_ID(0x000b6d02, uci_id_etm4),/* HiSilicon-Hip09 */ + /* + * Match all PIDs with ETM4 DEVARCH. No need for adding any of the new + * CPUs to the list here. + */ + CS_AMBA_MATCH_ALL_UCI(uci_id_etm4), {}, }; diff --git a/drivers/hwtracing/coresight/coresight-priv.h b/drivers/hwtracing/coresight/coresight-priv.h index 595ce5862056..72ec36c9232c 100644 --- a/drivers/hwtracing/coresight/coresight-priv.h +++ b/drivers/hwtracing/coresight/coresight-priv.h @@ -193,12 +193,27 @@ extern void coresight_remove_cti_ops(void); } /* coresight AMBA ID, full UCI structure: id table entry. */ -#define CS_AMBA_UCI_ID(pid, uci_ptr) \ +#define __CS_AMBA_UCI_ID(pid, m, uci_ptr) \ { \ .id = pid, \ - .mask = 0x000fffff, \ + .mask = m, \ .data = (void *)uci_ptr \ } +#define CS_AMBA_UCI_ID(pid, uci) __CS_AMBA_UCI_ID(pid, 0x000fffff, uci) +/* + * PIDR2[JEDEC], BIT(3) must be 1 (Read As One) to indicate that rest of the + * PIDR1, PIDR2 DES_* fields follow JEDEC encoding for the designer. Use that + * as a match value for blanket matching all devices in the given CoreSight + * device type and architecture. + */ +#define PIDR2_JEDEC BIT(3) +#define PID_PIDR2_JEDEC (PIDR2_JEDEC << 16) +/* + * Match all PIDs in a given CoreSight device type and architecture, defined + * by the uci. + */ +#define CS_AMBA_MATCH_ALL_UCI(uci) \ + __CS_AMBA_UCI_ID(PID_PIDR2_JEDEC, PID_PIDR2_JEDEC, uci) /* extract the data value from a UCI structure given amba_id pointer. */ static inline void *coresight_get_uci_data(const struct amba_id *id)
Instead of adding the PIDs forever to the list for the new CPUs, let us detect a component to be ETMv4 based on the CoreSight CID, DEVTYPE=PE_TRACE and DEVARCH=ETMv4. This is already done for some of the ETMs. We can extend the PID matching to match the PIDR2:JEDEC, BIT[3], which must be 1 (RA0) always. Link: https://lkml.kernel.org/r/20230317030501.1811905-1-anshuman.khandual@arm.com Cc: Anshuman Khandual <anshuman.khandual@arm.com> Cc: Rob Herring <robh+dt@kernel.org> Cc: frowand.list@gmail.com Cc: linux@armlinux.org.uk Cc: Mike Leach <mike.leach@linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> --- .../coresight/coresight-etm4x-core.c | 5 +++++ drivers/hwtracing/coresight/coresight-priv.h | 19 +++++++++++++++++-- 2 files changed, 22 insertions(+), 2 deletions(-)