| Message ID | 20230605174202.159278-1-sabiya.d@ti.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | arm64: dts: ti: k3-am69-sk: Enable MCU CPSW2G | expand |
On 23:12-20230605, sabiya.d@mistralsolutions.com wrote: > From: Dasnavis Sabiya <sabiya.d@ti.com> > > Add device tree support to enable MCU CPSW for AM69 SK > > Signed-off-by: Dasnavis Sabiya <sabiya.d@ti.com> Does'nt https://lore.kernel.org/linux-arm-kernel/20230602214937.2349545-6-nm@ti.com/ address this? I already CCed you, so do you care to ack instead? OR provide review comments so that I can improve the patch? > --- > arch/arm64/boot/dts/ti/k3-am69-sk.dts | 50 +++++++++++++++++++++++++++ > 1 file changed, 50 insertions(+) > > diff --git a/arch/arm64/boot/dts/ti/k3-am69-sk.dts b/arch/arm64/boot/dts/ti/k3-am69-sk.dts > index bc49ba534790..4b7d9280d76f 100644 > --- a/arch/arm64/boot/dts/ti/k3-am69-sk.dts > +++ b/arch/arm64/boot/dts/ti/k3-am69-sk.dts > @@ -104,6 +104,32 @@ vdd_sd_dv: regulator-tlv71033 { > }; > }; > > +&wkup_pmx0 { > + mcu_cpsw_pins_default: mcu-cpsw-pins-default { > + pinctrl-single,pins = < > + J784S4_WKUP_IOPAD(0x094, PIN_INPUT, 0) /* (A35) MCU_RGMII1_RD0 */ > + J784S4_WKUP_IOPAD(0x090, PIN_INPUT, 0) /* (B36) MCU_RGMII1_RD1 */ > + J784S4_WKUP_IOPAD(0x08c, PIN_INPUT, 0) /* (C36) MCU_RGMII1_RD2 */ > + J784S4_WKUP_IOPAD(0x088, PIN_INPUT, 0) /* (D36) MCU_RGMII1_RD3 */ > + J784S4_WKUP_IOPAD(0x084, PIN_INPUT, 0) /* (B37) MCU_RGMII1_RXC */ > + J784S4_WKUP_IOPAD(0x06c, PIN_INPUT, 0) /* (C37) MCU_RGMII1_RX_CTL */ > + J784S4_WKUP_IOPAD(0x07c, PIN_OUTPUT, 0) /* (D37) MCU_RGMII1_TD0 */ > + J784S4_WKUP_IOPAD(0x078, PIN_OUTPUT, 0) /* (D38) MCU_RGMII1_TD1 */ > + J784S4_WKUP_IOPAD(0x074, PIN_OUTPUT, 0) /* (E37) MCU_RGMII1_TD2 */ > + J784S4_WKUP_IOPAD(0x070, PIN_OUTPUT, 0) /* (E38) MCU_RGMII1_TD3 */ > + J784S4_WKUP_IOPAD(0x080, PIN_OUTPUT, 0) /* (E36) MCU_RGMII1_TXC */ > + J784S4_WKUP_IOPAD(0x068, PIN_OUTPUT, 0) /* (C38) MCU_RGMII1_TX_CTL */ > + >; > + }; > + > + mcu_mdio_pins_default: mcu-mdio-pins-default { > + pinctrl-single,pins = < > + J784S4_WKUP_IOPAD(0x09c, PIN_OUTPUT, 0) /* (A36) MCU_MDIO0_MDC */ > + J784S4_WKUP_IOPAD(0x098, PIN_INPUT, 0) /* (B35) MCU_MDIO0_MDIO */ > + >; > + }; > +}; > + > &main_pmx0 { > main_uart8_pins_default: main-uart8-pins-default { > pinctrl-single,pins = < > @@ -178,3 +204,27 @@ &main_sdhci1 { > &main_gpio0 { > status = "okay"; > }; > + > +&mcu_cpsw { > + status = "okay"; > + pinctrl-names = "default"; > + pinctrl-0 = <&mcu_cpsw_pins_default>; > +}; > + > +&davinci_mdio { > + pinctrl-names = "default"; > + pinctrl-0 = <&mcu_mdio_pins_default>; > + > + mcu_phy0: ethernet-phy@0 { > + reg = <0>; > + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; > + ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; > + ti,min-output-impedance; > + }; > +}; > + > +&mcu_cpsw_port1 { > + status = "okay"; > + phy-mode = "rgmii-rxid"; > + phy-handle = <&mcu_phy0>; > +}; > -- > 2.25.1 >
diff --git a/arch/arm64/boot/dts/ti/k3-am69-sk.dts b/arch/arm64/boot/dts/ti/k3-am69-sk.dts index bc49ba534790..4b7d9280d76f 100644 --- a/arch/arm64/boot/dts/ti/k3-am69-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am69-sk.dts @@ -104,6 +104,32 @@ vdd_sd_dv: regulator-tlv71033 { }; }; +&wkup_pmx0 { + mcu_cpsw_pins_default: mcu-cpsw-pins-default { + pinctrl-single,pins = < + J784S4_WKUP_IOPAD(0x094, PIN_INPUT, 0) /* (A35) MCU_RGMII1_RD0 */ + J784S4_WKUP_IOPAD(0x090, PIN_INPUT, 0) /* (B36) MCU_RGMII1_RD1 */ + J784S4_WKUP_IOPAD(0x08c, PIN_INPUT, 0) /* (C36) MCU_RGMII1_RD2 */ + J784S4_WKUP_IOPAD(0x088, PIN_INPUT, 0) /* (D36) MCU_RGMII1_RD3 */ + J784S4_WKUP_IOPAD(0x084, PIN_INPUT, 0) /* (B37) MCU_RGMII1_RXC */ + J784S4_WKUP_IOPAD(0x06c, PIN_INPUT, 0) /* (C37) MCU_RGMII1_RX_CTL */ + J784S4_WKUP_IOPAD(0x07c, PIN_OUTPUT, 0) /* (D37) MCU_RGMII1_TD0 */ + J784S4_WKUP_IOPAD(0x078, PIN_OUTPUT, 0) /* (D38) MCU_RGMII1_TD1 */ + J784S4_WKUP_IOPAD(0x074, PIN_OUTPUT, 0) /* (E37) MCU_RGMII1_TD2 */ + J784S4_WKUP_IOPAD(0x070, PIN_OUTPUT, 0) /* (E38) MCU_RGMII1_TD3 */ + J784S4_WKUP_IOPAD(0x080, PIN_OUTPUT, 0) /* (E36) MCU_RGMII1_TXC */ + J784S4_WKUP_IOPAD(0x068, PIN_OUTPUT, 0) /* (C38) MCU_RGMII1_TX_CTL */ + >; + }; + + mcu_mdio_pins_default: mcu-mdio-pins-default { + pinctrl-single,pins = < + J784S4_WKUP_IOPAD(0x09c, PIN_OUTPUT, 0) /* (A36) MCU_MDIO0_MDC */ + J784S4_WKUP_IOPAD(0x098, PIN_INPUT, 0) /* (B35) MCU_MDIO0_MDIO */ + >; + }; +}; + &main_pmx0 { main_uart8_pins_default: main-uart8-pins-default { pinctrl-single,pins = < @@ -178,3 +204,27 @@ &main_sdhci1 { &main_gpio0 { status = "okay"; }; + +&mcu_cpsw { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_cpsw_pins_default>; +}; + +&davinci_mdio { + pinctrl-names = "default"; + pinctrl-0 = <&mcu_mdio_pins_default>; + + mcu_phy0: ethernet-phy@0 { + reg = <0>; + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; + ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; + ti,min-output-impedance; + }; +}; + +&mcu_cpsw_port1 { + status = "okay"; + phy-mode = "rgmii-rxid"; + phy-handle = <&mcu_phy0>; +};