From patchwork Tue Jun 6 12:07:50 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Shavit X-Patchwork-Id: 13269062 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0CB6FC77B7A for ; Tue, 6 Jun 2023 12:11:28 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:From:Subject:Message-ID: References:Mime-Version:In-Reply-To:Date:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=m3iVVhJf6FbNyosEA6yGuZ8dmzh+EXNONqmaR1NJpO0=; b=mqsdM7+DAMUqpslQytfPJkbd/T ICjOljbeAdU2cDbbvYwv/ppDep7rdEMe+eIYgSoRvix6fz7oqye7Za1OXmfF9ZwpnH/So7NHGV6ls y3c2M+Knjz6GmTYXLFy7Zep0m7fNX17fYStMQeK7zG6voqH+R956vlPO0HLQVBaRn/scF87CLZFyi 2Ck+qRm1JMInSADscF2RxAQ9I5cumwpzfgH/bJpp+BStPHKTpLxpaDqrSQuTjvlEmgQnxq9p3/pj+ zTDjuDGUioOFyKAs90ng1ZRazXLkSpH7U4k5c9DDiHL9C8mZctG8EVa8xNg6MbbeUWHapsezbqVKJ vVj0etSg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1q6VWg-001ZbF-0u; Tue, 06 Jun 2023 12:11:02 +0000 Received: from mail-yb1-xb4a.google.com ([2607:f8b0:4864:20::b4a]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1q6VWd-001ZYo-1b for linux-arm-kernel@lists.infradead.org; Tue, 06 Jun 2023 12:11:00 +0000 Received: by mail-yb1-xb4a.google.com with SMTP id 3f1490d57ef6-ba8337ade1cso9622573276.2 for ; Tue, 06 Jun 2023 05:10:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20221208; t=1686053458; x=1688645458; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=e/IPHrVLjUq2s1o0Kk8jlOX8iem0l8MY258dkWJhSSA=; b=VZ4aVUegMrv+4Q6yvYwHunY/3cwuUlcr0h58VcDyy+whkFdBNoq1bmH2cIlw3NPTGf 2xwwiPuSrWUGDBls3d7jNYpe94klnR35TS5OkpOjjZPOxAO8MIWR85bzh29QZGu9r6vq Uhrp4oqPT2o6ewJtPDlh64Ybaq2kCogm4tvMgZDNn5hii7e3Sp7nkxS2CPQ+QqPKUqO2 jr7HF72nwtGIZwbU2rVIDb/0fXNIWezbdzedeFrmGi0/fABER6IwQMRfR22nwYnhBjrI RYCBaFffmg4sgiF4vWOkI7rmUWylAkhG7nKO4jBF3BV258AG4UrAU6eDZogjLom8Cb8J fe7Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686053458; x=1688645458; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=e/IPHrVLjUq2s1o0Kk8jlOX8iem0l8MY258dkWJhSSA=; b=gj7o9nFISbVwcqs+IzyFTetQ83xaQuu9q/hW91yraw8AKYqQ3UpWagb6wSEZuB5Rfe 1bzr+kYtRY7kSEtwveKtKtLp8LQaa662N4vVQ0zzDPLhwR4v21PvyviewdnHyyZ/xPNZ WbGXYjFRchbAhlNRIR/wdRLum2jIFAQeX+pnbAC22Uim8L6CXDQ9d0p5H4jFAOo8RxH4 6CWtW9JDuMt2Nc3InJINJFmDeTFNTTFG4cE76D8Kqeta006VOmD5mhlYBhXl6xMlNa8u 9WLac39A+btK5O1f2gSeg6OwpnWtH/nj88ntcEK1l8UW45/AICNKUISfjjEww0jtUV4r HAMA== X-Gm-Message-State: AC+VfDxyFcMHLaRMxAZDOVrzr66I3HbMXhJAEFFZ4vGe5g/HdYhS/381 FCZuxRwNzZtWgnOHbJHxOvV28BSe4yDf X-Google-Smtp-Source: ACHHUZ7wQ2cnghC4sSj2hPvQ7d1hwPGvVMm7khlu49LtLrhV/uxm381LyvtDF8uhJajK7hUiXOUQxpnGItxh X-Received: from mshavit.ntc.corp.google.com ([2401:fa00:95:20c:a615:63d5:b54e:6919]) (user=mshavit job=sendgmr) by 2002:a05:6902:1183:b0:ba7:7478:195f with SMTP id m3-20020a056902118300b00ba77478195fmr620081ybu.13.1686053458202; Tue, 06 Jun 2023 05:10:58 -0700 (PDT) Date: Tue, 6 Jun 2023 20:07:50 +0800 In-Reply-To: <20230606120854.4170244-1-mshavit@google.com> Mime-Version: 1.0 References: <20230606120854.4170244-1-mshavit@google.com> X-Mailer: git-send-email 2.41.0.rc0.172.g3f132b7071-goog Message-ID: <20230606120854.4170244-15-mshavit@google.com> Subject: [PATCH v2 14/18] iommu/arm-smmu-v3: Support domains with shared CDs From: Michael Shavit To: Will Deacon , Robin Murphy , Joerg Roedel Cc: Michael Shavit , jean-philippe@linaro.org, nicolinc@nvidia.com, jgg@nvidia.com, baolu.lu@linux.intel.com, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, linux-kernel@vger.kernel.org X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230606_051059_537440_02B3851A X-CRM114-Status: GOOD ( 16.42 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org SVA may attach a CD to masters that have different upstream SMMU devices. The arm_smmu_domain structure can only be attached to a single upstream SMMU device however. To work around this limitation, we propose an ARM_SMMU_DOMAIN_S1_SHARED domain type for domains that attach a CD shared across with arm_smmu_domains (each attached to a different upstream SMMU device). Signed-off-by: Michael Shavit --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 26 ++++++++++++++++----- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 2 ++ 2 files changed, 22 insertions(+), 6 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index b7f834dde85d1..69b1d09fd0284 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -965,6 +965,20 @@ void arm_smmu_tlb_inv_asid(struct arm_smmu_device *smmu, u16 asid) arm_smmu_cmdq_issue_cmd_with_sync(smmu, &cmd); } +static struct arm_smmu_ctx_desc *arm_smmu_get_cd(struct arm_smmu_domain *domain) +{ + if (domain->stage == ARM_SMMU_DOMAIN_S1_SHARED_CD) + return domain->shared_cd; + else + return &domain->cd; +} + +static bool arm_smmu_is_s1_domain(struct arm_smmu_domain *domain) +{ + return domain->stage == ARM_SMMU_DOMAIN_S1_SHARED_CD || + domain->stage == ARM_SMMU_DOMAIN_S1; +} + /* master may be null */ static void arm_smmu_sync_cd(struct arm_smmu_master *master, int ssid, bool leaf) @@ -1887,8 +1901,8 @@ static void arm_smmu_tlb_inv_context(void *cookie) * insertion to guarantee those are observed before the TLBI. Do be * careful, 007. */ - if (smmu_domain->stage == ARM_SMMU_DOMAIN_S1) { - arm_smmu_tlb_inv_asid(smmu, smmu_domain->cd.asid); + if (arm_smmu_is_s1_domain(smmu_domain)) { + arm_smmu_tlb_inv_asid(smmu, arm_smmu_get_cd(smmu_domain)->asid); } else { cmd.opcode = CMDQ_OP_TLBI_S12_VMALL; cmd.tlbi.vmid = smmu_domain->s2_cfg.vmid; @@ -1968,10 +1982,10 @@ static void arm_smmu_tlb_inv_range_domain(unsigned long iova, size_t size, }, }; - if (smmu_domain->stage == ARM_SMMU_DOMAIN_S1) { + if (arm_smmu_is_s1_domain(smmu_domain)) { cmd.opcode = smmu_domain->smmu->features & ARM_SMMU_FEAT_E2H ? CMDQ_OP_TLBI_EL2_VA : CMDQ_OP_TLBI_NH_VA; - cmd.tlbi.asid = smmu_domain->cd.asid; + cmd.tlbi.asid = arm_smmu_get_cd(smmu_domain)->asid; } else { cmd.opcode = CMDQ_OP_TLBI_S2_IPA; cmd.tlbi.vmid = smmu_domain->s2_cfg.vmid; @@ -2549,7 +2563,7 @@ static int arm_smmu_set_dev_pasid(struct iommu_domain *domain, return -ENODEV; } - if (smmu_domain->stage != ARM_SMMU_DOMAIN_S1) { + if (!arm_smmu_is_s1_domain(smmu_domain)) { dev_err(dev, "set_dev_pasid only supports stage 1 domains\n"); return -EINVAL; } @@ -2575,7 +2589,7 @@ static int arm_smmu_set_dev_pasid(struct iommu_domain *domain, */ mutex_lock(&arm_smmu_asid_lock); ret = arm_smmu_write_ctx_desc(master->smmu, master->s1_cfg, master, - pasid, &smmu_domain->cd); + pasid, arm_smmu_get_cd(smmu_domain)); if (ret) { mutex_unlock(&arm_smmu_asid_lock); kfree(attached_domain); diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h index 3525d60668c23..4ac69427abf1c 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -713,6 +713,7 @@ struct arm_smmu_master { /* SMMU private data for an IOMMU domain */ enum arm_smmu_domain_stage { ARM_SMMU_DOMAIN_S1 = 0, + ARM_SMMU_DOMAIN_S1_SHARED_CD, ARM_SMMU_DOMAIN_S2, ARM_SMMU_DOMAIN_NESTED, ARM_SMMU_DOMAIN_BYPASS, @@ -728,6 +729,7 @@ struct arm_smmu_domain { enum arm_smmu_domain_stage stage; union { struct arm_smmu_ctx_desc cd; + struct arm_smmu_ctx_desc *shared_cd; struct arm_smmu_s2_cfg s2_cfg; };