From patchwork Tue Jun 6 15:38:19 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tim Harvey X-Patchwork-Id: 13269398 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BA4DFC7EE24 for ; Tue, 6 Jun 2023 15:39:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-Id:Date:Subject:Cc :To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=Hr9g2vFc/MMRH2zVD9IrWbz8G8h51tBjoMWsu8mogEw=; b=WBWiEvqSJkvi2G CtlQnuZn3MPHdKObcBVH30klPXLMMcfzHWKbNmM1nOjvDZJlP6NN0uq9T5yHtysTGRJHiV2Pp0nxY +CBwcSHJE1Gd86iT91/YXrtr4WN0AJON7M1HSUr2tESAvlG9tzVNYxMTHZyKdxqexr5l+m7W2gyJd C5SSgjFZNKc8exjh2/2K6vjXFvZs12FSoaUUeK1nJo6EI2G8Ai4coE4yX84AaQ1LjsakngUWmaELL R1+NBkF3XTZ5a7s+7yHI1mocpxByIuFsrgy7QN1ZRfeiR9D6d6bPdsttxmKhxuDvYLZCCkviSxbyZ lhQkRtvgq96p3F84I/jQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1q6YlR-002Gyp-1c; Tue, 06 Jun 2023 15:38:29 +0000 Received: from finn.gateworks.com ([108.161.129.64] helo=finn.localdomain) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1q6YlO-002Gxc-2V for linux-arm-kernel@lists.infradead.org; Tue, 06 Jun 2023 15:38:27 +0000 Received: from 068-189-091-139.biz.spectrum.com ([68.189.91.139] helo=tharvey.pdc.gateworks.com) by finn.localdomain with esmtp (Exim 4.93) (envelope-from ) id 1q6YlJ-0067oT-EH; Tue, 06 Jun 2023 15:38:21 +0000 From: Tim Harvey To: linux-arm-kernel@lists.infradead.org Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Tim Harvey Subject: [PATCH] arm64: dts: imx8mm-venice-gw7904: enable UART1 hardware flow control Date: Tue, 6 Jun 2023 08:38:19 -0700 Message-Id: <20230606153819.1449257-1-tharvey@gateworks.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230606_083826_810217_983B624C X-CRM114-Status: UNSURE ( 9.77 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On the GW7904 uart1 can use UART3_TX/RX for hardware flow control which was the desired default configuration. Remove uart3 and configure uart1 for hardware flow control. Signed-off-by: Tim Harvey --- .../dts/freescale/imx8mm-venice-gw7904.dts | 18 ++++-------------- 1 file changed, 4 insertions(+), 14 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7904.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7904.dts index 93088fa1c3b9..c12e3f4f800f 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7904.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7904.dts @@ -636,6 +636,8 @@ &pgc_mipi { &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; + cts-gpios = <&gpio5 26 GPIO_ACTIVE_LOW>; + rts-gpios = <&gpio5 27 GPIO_ACTIVE_LOW>; status = "okay"; }; @@ -646,13 +648,6 @@ &uart2 { status = "okay"; }; -/* off-board RS232 */ -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - status = "okay"; -}; - &usbotg1 { dr_mode = "host"; disable-over-current; @@ -814,6 +809,8 @@ pinctrl_uart1: uart1grp { fsl,pins = < MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140 + MX8MM_IOMUXC_UART3_RXD_GPIO5_IO26 0x140 /* CTS# in */ + MX8MM_IOMUXC_UART3_TXD_GPIO5_IO27 0x140 /* RTS# out */ >; }; @@ -824,13 +821,6 @@ MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 >; }; - pinctrl_uart3: uart3grp { - fsl,pins = < - MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140 - MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140 - >; - }; - pinctrl_usdhc2: usdhc2grp { fsl,pins = < MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190