| Message ID | 20230607083139.3498788-2-ilkka@os.amperecomputing.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | perf: ampere: Add support for Ampere SoC PMUs | expand |
> -----Original Message----- > From: Ilkka Koskinen <ilkka@os.amperecomputing.com> > Sent: Wednesday, June 7, 2023 3:32 PM > To: Jonathan Corbet <corbet@lwn.net>; Will Deacon <will@kernel.org>; Mark > Rutland <mark.rutland@arm.com>; Besar Wicaksono > <bwicaksono@nvidia.com>; Suzuki K Poulose <suzuki.poulose@arm.com>; > Robin Murphy <robin.murphy@arm.com> > Cc: linux-doc@vger.kernel.org; linux-kernel@vger.kernel.org; linux-arm- > kernel@lists.infradead.org; Ilkka Koskinen <ilkka@os.amperecomputing.com> > Subject: [PATCH v3 1/4] perf: arm_cspmu: Split 64-bit write to 32-bit writes > > External email: Use caution opening links or attachments > > > Split the 64-bit register accesses if 64-bit access is not supported > by the PMU. > > Signed-off-by: Ilkka Koskinen <ilkka@os.amperecomputing.com> > --- > drivers/perf/arm_cspmu/arm_cspmu.c | 5 ++++- > 1 file changed, 4 insertions(+), 1 deletion(-) > > diff --git a/drivers/perf/arm_cspmu/arm_cspmu.c > b/drivers/perf/arm_cspmu/arm_cspmu.c > index a3f1c410b417..f8b4a149eb88 100644 > --- a/drivers/perf/arm_cspmu/arm_cspmu.c > +++ b/drivers/perf/arm_cspmu/arm_cspmu.c > @@ -702,7 +702,10 @@ static void arm_cspmu_write_counter(struct > perf_event *event, u64 val) > if (use_64b_counter_reg(cspmu)) { > offset = counter_offset(sizeof(u64), event->hw.idx); > > - writeq(val, cspmu->base1 + offset); > + if (supports_64bit_atomics(cspmu)) Looks good to me, but this function was recently replaced by arm_cspmu::has_atomic_dword. Please rebase the patch. Thanks, Besar > + writeq(val, cspmu->base1 + offset); > + else > + lo_hi_writeq(val, cspmu->base1 + offset); > } else { > offset = counter_offset(sizeof(u32), event->hw.idx); > > -- > 2.40.1
Hi Besar, On Tue, 20 Jun 2023, Besar Wicaksono wrote: >> -----Original Message----- >> From: Ilkka Koskinen <ilkka@os.amperecomputing.com> >> Sent: Wednesday, June 7, 2023 3:32 PM >> To: Jonathan Corbet <corbet@lwn.net>; Will Deacon <will@kernel.org>; Mark >> Rutland <mark.rutland@arm.com>; Besar Wicaksono >> <bwicaksono@nvidia.com>; Suzuki K Poulose <suzuki.poulose@arm.com>; >> Robin Murphy <robin.murphy@arm.com> >> Cc: linux-doc@vger.kernel.org; linux-kernel@vger.kernel.org; linux-arm- >> kernel@lists.infradead.org; Ilkka Koskinen <ilkka@os.amperecomputing.com> >> Subject: [PATCH v3 1/4] perf: arm_cspmu: Split 64-bit write to 32-bit writes >> >> External email: Use caution opening links or attachments >> >> >> Split the 64-bit register accesses if 64-bit access is not supported >> by the PMU. >> >> Signed-off-by: Ilkka Koskinen <ilkka@os.amperecomputing.com> >> --- >> drivers/perf/arm_cspmu/arm_cspmu.c | 5 ++++- >> 1 file changed, 4 insertions(+), 1 deletion(-) >> >> diff --git a/drivers/perf/arm_cspmu/arm_cspmu.c >> b/drivers/perf/arm_cspmu/arm_cspmu.c >> index a3f1c410b417..f8b4a149eb88 100644 >> --- a/drivers/perf/arm_cspmu/arm_cspmu.c >> +++ b/drivers/perf/arm_cspmu/arm_cspmu.c >> @@ -702,7 +702,10 @@ static void arm_cspmu_write_counter(struct >> perf_event *event, u64 val) >> if (use_64b_counter_reg(cspmu)) { >> offset = counter_offset(sizeof(u64), event->hw.idx); >> >> - writeq(val, cspmu->base1 + offset); >> + if (supports_64bit_atomics(cspmu)) > > Looks good to me, but this function was recently replaced by > arm_cspmu::has_atomic_dword. Please rebase the patch. Sure, I do that. Cheers, Ilkka > > Thanks, > Besar > >> + writeq(val, cspmu->base1 + offset); >> + else >> + lo_hi_writeq(val, cspmu->base1 + offset); >> } else { >> offset = counter_offset(sizeof(u32), event->hw.idx); >> >> -- >> 2.40.1 > >
diff --git a/drivers/perf/arm_cspmu/arm_cspmu.c b/drivers/perf/arm_cspmu/arm_cspmu.c index a3f1c410b417..f8b4a149eb88 100644 --- a/drivers/perf/arm_cspmu/arm_cspmu.c +++ b/drivers/perf/arm_cspmu/arm_cspmu.c @@ -702,7 +702,10 @@ static void arm_cspmu_write_counter(struct perf_event *event, u64 val) if (use_64b_counter_reg(cspmu)) { offset = counter_offset(sizeof(u64), event->hw.idx); - writeq(val, cspmu->base1 + offset); + if (supports_64bit_atomics(cspmu)) + writeq(val, cspmu->base1 + offset); + else + lo_hi_writeq(val, cspmu->base1 + offset); } else { offset = counter_offset(sizeof(u32), event->hw.idx);
Split the 64-bit register accesses if 64-bit access is not supported by the PMU. Signed-off-by: Ilkka Koskinen <ilkka@os.amperecomputing.com> --- drivers/perf/arm_cspmu/arm_cspmu.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-)