@@ -27,6 +27,115 @@ aliases {
rdma1 = &rdma1;
};
+ cci: cci {
+ compatible = "mediatek,mt8186-cci";
+ clocks = <&mcusys CLK_MCU_ARMPLL_BUS_SEL>,
+ <&apmixedsys CLK_APMIXED_MAINPLL>;
+ clock-names = "cci", "intermediate";
+ operating-points-v2 = <&cci_opp>;
+ };
+
+ cci_opp: opp-table-cci {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ cci_opp_0: opp-500000000 {
+ opp-hz = /bits/ 64 <500000000>;
+ opp-microvolt = <600000>;
+ opp-level = <15>;
+ };
+
+ cci_opp_1: opp-560000000 {
+ opp-hz = /bits/ 64 <560000000>;
+ opp-microvolt = <675000>;
+ opp-level = <14>;
+ };
+
+ cci_opp_2: opp-612000000 {
+ opp-hz = /bits/ 64 <612000000>;
+ opp-microvolt = <693750>;
+ opp-level = <13>;
+ };
+
+ cci_opp_3: opp-682000000 {
+ opp-hz = /bits/ 64 <682000000>;
+ opp-microvolt = <718750>;
+ opp-level = <12>;
+ };
+
+ cci_opp_4: opp-752000000 {
+ opp-hz = /bits/ 64 <752000000>;
+ opp-microvolt = <743750>;
+ opp-level = <11>;
+ };
+
+ cci_opp_5: opp-822000000 {
+ opp-hz = /bits/ 64 <822000000>;
+ opp-microvolt = <768750>;
+ opp-level = <10>;
+ };
+
+ cci_opp_6: opp-875000000 {
+ opp-hz = /bits/ 64 <875000000>;
+ opp-microvolt = <781250>;
+ opp-level = <9>;
+ };
+
+ cci_opp_7: opp-927000000 {
+ opp-hz = /bits/ 64 <927000000>;
+ opp-microvolt = <800000>;
+ opp-level = <8>;
+ };
+
+ cci_opp_8: opp-980000000 {
+ opp-hz = /bits/ 64 <980000000>;
+ opp-microvolt = <818750>;
+ opp-level = <7>;
+ };
+
+ cci_opp_9: opp-1050000000 {
+ opp-hz = /bits/ 64 <1050000000>;
+ opp-microvolt = <843750>;
+ opp-level = <6>;
+ };
+
+ cci_opp_10: opp-1120000000 {
+ opp-hz = /bits/ 64 <1120000000>;
+ opp-microvolt = <862500>;
+ opp-level = <5>;
+ };
+
+ cci_opp_11: opp-1155000000 {
+ opp-hz = /bits/ 64 <1155000000>;
+ opp-microvolt = <887500>;
+ opp-level = <4>;
+ };
+
+ cci_opp_12: opp-1190000000 {
+ opp-hz = /bits/ 64 <1190000000>;
+ opp-microvolt = <906250>;
+ opp-level = <3>;
+ };
+
+ cci_opp_13: opp-1260000000 {
+ opp-hz = /bits/ 64 <1260000000>;
+ opp-microvolt = <950000>;
+ opp-level = <2>;
+ };
+
+ cci_opp_14: opp-1330000000 {
+ opp-hz = /bits/ 64 <1330000000>;
+ opp-microvolt = <993750>;
+ opp-level = <1>;
+ };
+
+ cci_opp_15: opp-1400000000 {
+ opp-hz = /bits/ 64 <1400000000>;
+ opp-microvolt = <1031250>;
+ opp-level = <0>;
+ };
+ };
+
cpus {
#address-cells = <1>;
#size-cells = <0>;
@@ -83,6 +192,7 @@ cpu0: cpu@0 {
d-cache-sets = <128>;
next-level-cache = <&l2_0>;
#cooling-cells = <2>;
+ mediatek,cci = <&cci>;
};
cpu1: cpu@100 {
@@ -101,6 +211,7 @@ cpu1: cpu@100 {
d-cache-sets = <128>;
next-level-cache = <&l2_0>;
#cooling-cells = <2>;
+ mediatek,cci = <&cci>;
};
cpu2: cpu@200 {
@@ -119,6 +230,7 @@ cpu2: cpu@200 {
d-cache-sets = <128>;
next-level-cache = <&l2_0>;
#cooling-cells = <2>;
+ mediatek,cci = <&cci>;
};
cpu3: cpu@300 {
@@ -137,6 +249,7 @@ cpu3: cpu@300 {
d-cache-sets = <128>;
next-level-cache = <&l2_0>;
#cooling-cells = <2>;
+ mediatek,cci = <&cci>;
};
cpu4: cpu@400 {
@@ -155,6 +268,7 @@ cpu4: cpu@400 {
d-cache-sets = <128>;
next-level-cache = <&l2_0>;
#cooling-cells = <2>;
+ mediatek,cci = <&cci>;
};
cpu5: cpu@500 {
@@ -173,6 +287,7 @@ cpu5: cpu@500 {
d-cache-sets = <128>;
next-level-cache = <&l2_0>;
#cooling-cells = <2>;
+ mediatek,cci = <&cci>;
};
cpu6: cpu@600 {
@@ -191,6 +306,7 @@ cpu6: cpu@600 {
d-cache-sets = <256>;
next-level-cache = <&l2_1>;
#cooling-cells = <2>;
+ mediatek,cci = <&cci>;
};
cpu7: cpu@700 {
@@ -209,6 +325,7 @@ cpu7: cpu@700 {
d-cache-sets = <256>;
next-level-cache = <&l2_1>;
#cooling-cells = <2>;
+ mediatek,cci = <&cci>;
};
idle-states {
Add a device node for the CCI (cache coherent interconnect) and an OPP table for it. The OPP table was taken from the downstream ChromeOS kernel. Signed-off-by: Chen-Yu Tsai <wenst@chromium.org> --- arch/arm64/boot/dts/mediatek/mt8186.dtsi | 117 +++++++++++++++++++++++ 1 file changed, 117 insertions(+)