From patchwork Fri Jun 9 07:29:02 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chen-Yu Tsai X-Patchwork-Id: 13273329 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DCE39C7EE2E for ; Fri, 9 Jun 2023 07:29:43 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=xJMDyoV+utKxOzRddg8oK5mHgjDYCk+c/kH0Rb7UeNs=; b=NNypcTAhevAJl3 t64EOLDvNHA5MogHOghtT80mPvMDf8UoogcPEKA/1tLT/NIocva/90R10Vy1NADYDP+wu662A1apa 1FfxBhA/VzJPQJaZ1Wvga4rzowRVDpo8QcQRlcAydLDy38OlgGVtPkuMd4qDM38nH6NZnXm/8QiTP jKYmlC9x10YUYXQfzR7OpTOKBQOt3ffybOarQDiQnkDCnJowiljKoz/fStkNvFdhA5t74KKjYR06D GwkgaSv7ImoYz2dqzz9ifOpjvX13SKI2+ELwZYpXCiw+Ta07FTXFaIDHHj3n8peP9xeU1VRmns9xX jQSnkvB9o8f69lV5+MpA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1q7WYk-00C2Ug-3B; Fri, 09 Jun 2023 07:29:22 +0000 Received: from mail-oa1-x33.google.com ([2001:4860:4864:20::33]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1q7WYd-00C2Qn-2w for linux-arm-kernel@lists.infradead.org; Fri, 09 Jun 2023 07:29:18 +0000 Received: by mail-oa1-x33.google.com with SMTP id 586e51a60fabf-19f6f8c8283so455552fac.3 for ; Fri, 09 Jun 2023 00:29:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; t=1686295754; x=1688887754; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Fiqfy79Fm9eELrPZKhr0IzKYUTLKfOcN1zfjvWIor1U=; b=LxMNX7PgqJYg8YS2zT4J43YxXo9Sb8PLiIJ9k2lgNd1Xh5voESEHcivw8u8jtBBzP/ WiRjfyprxZi9kjfz9+meNBuo3OXBMaIc9u8YgtjYmT8e8l4RFqLi+LfeOuUoUm04yQKX bABGqbnX15cF3yKr5Ljr5dlBDIn9cA8v6Uc0Y= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686295754; x=1688887754; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Fiqfy79Fm9eELrPZKhr0IzKYUTLKfOcN1zfjvWIor1U=; b=Zd1Fr5bntLVWmNpYAhBDm5UGQOEg0c3GLW464sFn2ALLdLCPtw+CG0fCSlxfl7oyFe tpMYQUEkVdKV8dG4LzIAJ9nFV5jXbicNkxibgioU0jpNaV0iCGA5Xeo7uxxkEJ6QPuS4 jyxA9erw8T4TIuHRHsd3Hbu3pXf0yt1K/AWNxKRadaT0bWlAeTOyYgBAuPsXF04+IzG8 t/DfH3DTv1k7wMwD/xZNUITGMN+TVZH1otJ0wYGHMYRKbcTc9EURBC8zF4wdPo53dmIq RDz/sxKgcDmlVOFXccEeXVxXJPk5x1sz4xpFo71xRopgMCFdi+EZnqbLAmqs5Kb85jho s6Ig== X-Gm-Message-State: AC+VfDw2cOmFgyVNoU3yjheFMZAqqGCjq4Y7QSeZV+ZtzjNgTsohbGc1 ZExDSJF709ESgEslaLdJtx2SIA== X-Google-Smtp-Source: ACHHUZ501Ve/MgepNvdJuxacEzoyyJ1OpWSjaxrZfy48TfjQ3Y9Q5kePfUaxCgQyognbCgNex8NP+g== X-Received: by 2002:a05:6870:3505:b0:1a3:5de8:e78b with SMTP id k5-20020a056870350500b001a35de8e78bmr576923oah.21.1686295754188; Fri, 09 Jun 2023 00:29:14 -0700 (PDT) Received: from wenstp920.tpe.corp.google.com ([2401:fa00:1:10:c2ea:d8e4:1fe8:21f0]) by smtp.gmail.com with ESMTPSA id y9-20020a655a09000000b005287a0560c9sm2160283pgs.1.2023.06.09.00.29.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 09 Jun 2023 00:29:13 -0700 (PDT) From: Chen-Yu Tsai To: Matthias Brugger , AngeloGioacchino Del Regno Cc: Chen-Yu Tsai , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Rob Herring , Krzysztof Kozlowski , Conor Dooley Subject: [PATCH v2 1/4] arm64: dts: mediatek: mt8186: Add CCI node and CCI OPP table Date: Fri, 9 Jun 2023 15:29:02 +0800 Message-ID: <20230609072906.2784594-2-wenst@chromium.org> X-Mailer: git-send-email 2.41.0.162.gfafddb0af9-goog In-Reply-To: <20230609072906.2784594-1-wenst@chromium.org> References: <20230609072906.2784594-1-wenst@chromium.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230609_002915_948846_6842E0C1 X-CRM114-Status: GOOD ( 12.26 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add a device node for the CCI (cache coherent interconnect) and an OPP table for it. The OPP table was taken from the downstream ChromeOS kernel. Signed-off-by: Chen-Yu Tsai Reviewed-by: AngeloGioacchino Del Regno --- Angelo, I didn't pick up your Reviewed-by since I dropped the "opp-level" properties. arch/arm64/boot/dts/mediatek/mt8186.dtsi | 101 +++++++++++++++++++++++ 1 file changed, 101 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi index 8c02232cac38..93f3c45ba372 100644 --- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi @@ -27,6 +27,99 @@ aliases { rdma1 = &rdma1; }; + cci: cci { + compatible = "mediatek,mt8186-cci"; + clocks = <&mcusys CLK_MCU_ARMPLL_BUS_SEL>, + <&apmixedsys CLK_APMIXED_MAINPLL>; + clock-names = "cci", "intermediate"; + operating-points-v2 = <&cci_opp>; + }; + + cci_opp: opp-table-cci { + compatible = "operating-points-v2"; + opp-shared; + + cci_opp_0: opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <600000>; + }; + + cci_opp_1: opp-560000000 { + opp-hz = /bits/ 64 <560000000>; + opp-microvolt = <675000>; + }; + + cci_opp_2: opp-612000000 { + opp-hz = /bits/ 64 <612000000>; + opp-microvolt = <693750>; + }; + + cci_opp_3: opp-682000000 { + opp-hz = /bits/ 64 <682000000>; + opp-microvolt = <718750>; + }; + + cci_opp_4: opp-752000000 { + opp-hz = /bits/ 64 <752000000>; + opp-microvolt = <743750>; + }; + + cci_opp_5: opp-822000000 { + opp-hz = /bits/ 64 <822000000>; + opp-microvolt = <768750>; + }; + + cci_opp_6: opp-875000000 { + opp-hz = /bits/ 64 <875000000>; + opp-microvolt = <781250>; + }; + + cci_opp_7: opp-927000000 { + opp-hz = /bits/ 64 <927000000>; + opp-microvolt = <800000>; + }; + + cci_opp_8: opp-980000000 { + opp-hz = /bits/ 64 <980000000>; + opp-microvolt = <818750>; + }; + + cci_opp_9: opp-1050000000 { + opp-hz = /bits/ 64 <1050000000>; + opp-microvolt = <843750>; + }; + + cci_opp_10: opp-1120000000 { + opp-hz = /bits/ 64 <1120000000>; + opp-microvolt = <862500>; + }; + + cci_opp_11: opp-1155000000 { + opp-hz = /bits/ 64 <1155000000>; + opp-microvolt = <887500>; + }; + + cci_opp_12: opp-1190000000 { + opp-hz = /bits/ 64 <1190000000>; + opp-microvolt = <906250>; + }; + + cci_opp_13: opp-1260000000 { + opp-hz = /bits/ 64 <1260000000>; + opp-microvolt = <950000>; + }; + + cci_opp_14: opp-1330000000 { + opp-hz = /bits/ 64 <1330000000>; + opp-microvolt = <993750>; + }; + + cci_opp_15: opp-1400000000 { + opp-hz = /bits/ 64 <1400000000>; + opp-microvolt = <1031250>; + }; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -83,6 +176,7 @@ cpu0: cpu@0 { d-cache-sets = <128>; next-level-cache = <&l2_0>; #cooling-cells = <2>; + mediatek,cci = <&cci>; }; cpu1: cpu@100 { @@ -101,6 +195,7 @@ cpu1: cpu@100 { d-cache-sets = <128>; next-level-cache = <&l2_0>; #cooling-cells = <2>; + mediatek,cci = <&cci>; }; cpu2: cpu@200 { @@ -119,6 +214,7 @@ cpu2: cpu@200 { d-cache-sets = <128>; next-level-cache = <&l2_0>; #cooling-cells = <2>; + mediatek,cci = <&cci>; }; cpu3: cpu@300 { @@ -137,6 +233,7 @@ cpu3: cpu@300 { d-cache-sets = <128>; next-level-cache = <&l2_0>; #cooling-cells = <2>; + mediatek,cci = <&cci>; }; cpu4: cpu@400 { @@ -155,6 +252,7 @@ cpu4: cpu@400 { d-cache-sets = <128>; next-level-cache = <&l2_0>; #cooling-cells = <2>; + mediatek,cci = <&cci>; }; cpu5: cpu@500 { @@ -173,6 +271,7 @@ cpu5: cpu@500 { d-cache-sets = <128>; next-level-cache = <&l2_0>; #cooling-cells = <2>; + mediatek,cci = <&cci>; }; cpu6: cpu@600 { @@ -191,6 +290,7 @@ cpu6: cpu@600 { d-cache-sets = <256>; next-level-cache = <&l2_1>; #cooling-cells = <2>; + mediatek,cci = <&cci>; }; cpu7: cpu@700 { @@ -209,6 +309,7 @@ cpu7: cpu@700 { d-cache-sets = <256>; next-level-cache = <&l2_1>; #cooling-cells = <2>; + mediatek,cci = <&cci>; }; idle-states {