Message ID | 20230614065949.146187-15-anshuman.khandual@arm.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
Series | arm64/sysreg: Convert TRBE registers to automatic generation | expand |
On Wed, Jun 14, 2023 at 12:29:49PM +0530, Anshuman Khandual wrote: > This converts TRBIDR_EL1 register to automatic generation without > causing any functional change. Reviewed-by: Mark Brown <broonie@kernel.org>
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index 088831b6cf6c..1b71bbd8b4e0 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -241,14 +241,8 @@ /*** End of Statistical Profiling Extension ***/ -#define SYS_TRBIDR_EL1 sys_reg(3, 0, 9, 11, 7) - #define TRBSR_EL1_BSC_MASK GENMASK(5, 0) #define TRBSR_EL1_BSC_SHIFT 0 -#define TRBIDR_EL1_F BIT(5) -#define TRBIDR_EL1_P BIT(4) -#define TRBIDR_EL1_Align_MASK GENMASK(3, 0) -#define TRBIDR_EL1_Align_SHIFT 0 #define SYS_PMINTENSET_EL1 sys_reg(3, 0, 9, 14, 1) #define SYS_PMINTENCLR_EL1 sys_reg(3, 0, 9, 14, 2) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 4292e6014d2e..7f22faeaaba0 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -2264,3 +2264,16 @@ Sysreg TRBTRG_EL1 3 0 9 11 6 Res0 63:32 Field 31:0 TRG EndSysreg + +Sysreg TRBIDR_EL1 3 0 9 11 7 +Res0 63:12 +Enum 11:8 EA + 0b0000 NON_DESC + 0b0001 IGNORE + 0b0010 SERROR +EndEnum +Res0 7:6 +Field 5 F +Field 4 P +Field 3:0 Align +EndSysreg