| Message ID | 20230615144423.828698-2-privatesub2@gmail.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add support for Allwinner PWM on D1/T113s/R329 SoCs | expand |
Hey Aleksandr, On Thu, Jun 15, 2023 at 05:43:56PM +0300, Aleksandr Shubin wrote: > Allwinner's D1, T113-S3 and R329 SoCs have a new pwm > controller witch is different from the previous pwm-sun4i. > > D1 and T113s SoCs have one PWM controller with 8 channels. > R329 SoC has two PWM controllers in both power domains, one of > them has 9 channels (CPUX one) and the other has 6 (CPUS one). It would be good to note that the D1 and T113 are identical in terms of peripherals, they differ only in the architecture of the CPU core, and even share the majority of their DT. Because of that, using the same compatible makes sense. The R329 is a different SoC though, and should have a different compatible string added, especially as there is a difference in the number of channels. It would be fine to use the current compatible for the D1 as a fallback. The allwinner,pwm-channels property should probably only be allowed on the R329 and only allow the values of 6 & 9. > Add a device tree binding for them. > > Signed-off-by: Aleksandr Shubin <privatesub2@gmail.com> > --- > .../bindings/pwm/allwinner,sun20i-pwm.yaml | 70 +++++++++++++++++++ > 1 file changed, 70 insertions(+) > create mode 100644 Documentation/devicetree/bindings/pwm/allwinner,sun20i-pwm.yaml > > diff --git a/Documentation/devicetree/bindings/pwm/allwinner,sun20i-pwm.yaml b/Documentation/devicetree/bindings/pwm/allwinner,sun20i-pwm.yaml > new file mode 100644 > index 000000000000..e5f9cb2d5c4f > --- /dev/null > +++ b/Documentation/devicetree/bindings/pwm/allwinner,sun20i-pwm.yaml > @@ -0,0 +1,70 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/pwm/allwinner,sun20i-pwm.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Allwinner D1, T113-S3 and R329 PWM > + > +maintainers: > + - Chen-Yu Tsai <wens@csie.org> > + - Maxime Ripard <mripard@kernel.org> BTW, this should probably be you, since you have the hardware with this SoC. > + > +allOf: > + - $ref: pwm.yaml# > + > +properties: > + compatible: > + const: allwinner,sun20i-d1-pwm > + > + reg: > + maxItems: 1 > + > + "#pwm-cells": > + const: 3 > + > + clocks: > + items: > + - description: 24 MHz oscillator > + - description: Bus Clock > + > + clock-names: > + items: > + - const: hosc > + - const: bus > + > + resets: > + items: > + - description: module reset Don't need the items here, because there is only one. You can just do "maxItems: 1" instead. > + allwinner,pwm-channels: > + $ref: /schemas/types.yaml#/definitions/uint32 > + description: The number of PWM channels configured for this instance > + > +required: > + - compatible > + - reg > + - "#pwm-cells" > + - clocks > + - clock-names > + - resets > + - allwinner,pwm-channels Cheers, Conor.
On Fri, Jun 16, 2023 at 11:02:12AM +0300, Александр Шубин wrote: > чт, 15 июн. 2023 г. в 19:37, Conor Dooley <conor@kernel.org>: > > On Thu, Jun 15, 2023 at 05:43:56PM +0300, Aleksandr Shubin wrote: > > > Allwinner's D1, T113-S3 and R329 SoCs have a new pwm > > > controller witch is different from the previous pwm-sun4i. > > > > > > D1 and T113s SoCs have one PWM controller with 8 channels. > > > R329 SoC has two PWM controllers in both power domains, one of > > > them has 9 channels (CPUX one) and the other has 6 (CPUS one). > > > > It would be good to note that the D1 and T113 are identical in terms of > > peripherals, they differ only in the architecture of the CPU core, and > > even share the majority of their DT. Because of that, using the same > > compatible makes sense. > > The R329 is a different SoC though, and should have a different > > compatible string added, especially as there is a difference in the > > number of channels. It would be fine to use the current compatible for > > the D1 as a fallback. > > The allwinner,pwm-channels property should probably only be allowed on > > the R329 and only allow the values of 6 & 9. > > > Maybe would it be better to allow only 8 channels for D1 and only 6 and 9 > channels for R329? If you're on a D1, you don't need a dt property to tell you the number of channels, you already know it to be 8. Couple ways driver could implement that, for example: if the dt-binding requires the property on the R329, you could set 8 as the default and overwrite it if the property exists - which would only be permitted on the R329. Up to you.
diff --git a/Documentation/devicetree/bindings/pwm/allwinner,sun20i-pwm.yaml b/Documentation/devicetree/bindings/pwm/allwinner,sun20i-pwm.yaml new file mode 100644 index 000000000000..e5f9cb2d5c4f --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/allwinner,sun20i-pwm.yaml @@ -0,0 +1,70 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pwm/allwinner,sun20i-pwm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner D1, T113-S3 and R329 PWM + +maintainers: + - Chen-Yu Tsai <wens@csie.org> + - Maxime Ripard <mripard@kernel.org> + +allOf: + - $ref: pwm.yaml# + +properties: + compatible: + const: allwinner,sun20i-d1-pwm + + reg: + maxItems: 1 + + "#pwm-cells": + const: 3 + + clocks: + items: + - description: 24 MHz oscillator + - description: Bus Clock + + clock-names: + items: + - const: hosc + - const: bus + + resets: + items: + - description: module reset + + allwinner,pwm-channels: + $ref: /schemas/types.yaml#/definitions/uint32 + description: The number of PWM channels configured for this instance + +required: + - compatible + - reg + - "#pwm-cells" + - clocks + - clock-names + - resets + - allwinner,pwm-channels + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/sun20i-d1-ccu.h> + #include <dt-bindings/reset/sun20i-d1-ccu.h> + + pwm: pwm@2000c00 { + compatible = "allwinner,sun20i-d1-pwm"; + reg = <0x02000c00 0x400>; + clocks = <&dcxo>, <&ccu CLK_BUS_PWM>; + clock-names = "hosc", "bus"; + resets = <&ccu RST_BUS_PWM>; + allwinner,pwm-channels = <8>; + #pwm-cells = <0x3>; + }; + +...
Allwinner's D1, T113-S3 and R329 SoCs have a new pwm controller witch is different from the previous pwm-sun4i. D1 and T113s SoCs have one PWM controller with 8 channels. R329 SoC has two PWM controllers in both power domains, one of them has 9 channels (CPUX one) and the other has 6 (CPUS one). Add a device tree binding for them. Signed-off-by: Aleksandr Shubin <privatesub2@gmail.com> --- .../bindings/pwm/allwinner,sun20i-pwm.yaml | 70 +++++++++++++++++++ 1 file changed, 70 insertions(+) create mode 100644 Documentation/devicetree/bindings/pwm/allwinner,sun20i-pwm.yaml