From patchwork Mon Jun 26 09:52:23 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xianwei Zhao X-Patchwork-Id: 13292591 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5109DEB64DC for ; Mon, 26 Jun 2023 09:53:36 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=9iTFGO58wQXW5p8vxrVGwcLISwsLZoqqu5ZFwVW9luE=; b=aRK2YYgAizU1+I PeFw5Beo1Yw+RVTGy62Q42Ec7o9eP61OBTjFiCBkvrGxG+8/zQgNXd1AOAJ05U2SFuoGmLFZTslW8 LOS6NdVBQ+WfxyMurAt+snc4IYoIxn3slhZo8HLi6gDKyhT0VsLaW94CtJUNQaUvgH6MRir8sVpMG ptFxEO57nS8Y/Puqd8PWdf+RIvbw01OWrneVZi8xHzlMaMr5GS7+HGOuXOcR/Y8IjFgKuF1IKLQJo w3JYSQvwEo76s3ZBC8m9xS4H1ItglMRMJ2d3sFCNtIyqSRywPrwAkuaxGxuC/I/KZn8gp3y5d0DIE hoAM8K+qTZCRz6RJqDCA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qDiuB-009m8W-2O; Mon, 26 Jun 2023 09:53:07 +0000 Received: from mail-sh.amlogic.com ([58.32.228.43]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1qDitx-009m2q-2w; Mon, 26 Jun 2023 09:52:55 +0000 Received: from droid01-cd.amlogic.com (10.98.11.200) by mail-sh.amlogic.com (10.18.11.5) with Microsoft SMTP Server id 15.1.2507.13; Mon, 26 Jun 2023 17:52:29 +0800 From: Xianwei Zhao To: , , , CC: Catalin Marinas , Will Deacon , Neil Armstrong , Kevin Hilman , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Xianwei Zhao Subject: [PATCH 2/2] arm64: dts: add support for T7 based Amlogic AN400 Date: Mon, 26 Jun 2023 17:52:23 +0800 Message-ID: <20230626095223.721011-3-xianwei.zhao@amlogic.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20230626095223.721011-1-xianwei.zhao@amlogic.com> References: <20230626095223.721011-1-xianwei.zhao@amlogic.com> MIME-Version: 1.0 X-Originating-IP: [10.98.11.200] X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230626_025253_953488_32E25CE2 X-CRM114-Status: GOOD ( 13.76 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Amlogic T7 is an advanced application processor designed for smart display. Add basic support for the T7 based Amlogic AN400 board, which describes the following components: CPU, GIC, IRQ, Timer, UART. It's capable of booting up into the serial console. Signed-off-by: Xianwei Zhao --- arch/arm64/boot/dts/amlogic/Makefile | 1 + .../dts/amlogic/amlogic-t7-a311d2-an400.dts | 30 ++++ arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi | 156 ++++++++++++++++++ 3 files changed, 187 insertions(+) create mode 100644 arch/arm64/boot/dts/amlogic/amlogic-t7-a311d2-an400.dts create mode 100644 arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi diff --git a/arch/arm64/boot/dts/amlogic/Makefile b/arch/arm64/boot/dts/amlogic/Makefile index 6f61798a109f..99299731f5d4 100644 --- a/arch/arm64/boot/dts/amlogic/Makefile +++ b/arch/arm64/boot/dts/amlogic/Makefile @@ -1,5 +1,6 @@ # SPDX-License-Identifier: GPL-2.0 dtb-$(CONFIG_ARCH_MESON) += amlogic-c3-c302x-aw409.dtb +dtb-$(CONFIG_ARCH_MESON) += amlogic-t7-a311d2-an400.dtb dtb-$(CONFIG_ARCH_MESON) += meson-a1-ad401.dtb dtb-$(CONFIG_ARCH_MESON) += meson-axg-jethome-jethub-j100.dtb dtb-$(CONFIG_ARCH_MESON) += meson-axg-jethome-jethub-j110-rev-2.dtb diff --git a/arch/arm64/boot/dts/amlogic/amlogic-t7-a311d2-an400.dts b/arch/arm64/boot/dts/amlogic/amlogic-t7-a311d2-an400.dts new file mode 100644 index 000000000000..7ce1975b99e4 --- /dev/null +++ b/arch/arm64/boot/dts/amlogic/amlogic-t7-a311d2-an400.dts @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Amlogic, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "amlogic-t7.dtsi" + +/ { + model = "Amlogic A311D2 AN400 Development Board"; + compatible = "amlogic,an400", "amlogic,t7"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + serial0 = &uart_a; + }; + + memory@0 { + device_type = "memory"; + linux,usable-memory = <0x00000000 0x00000000 0x00000000 0xE0000000 + 0x00000001 0x00000000 0x00000000 0x20000000>; + }; +}; + +&uart_a { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi b/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi new file mode 100644 index 000000000000..d3ee864f0d40 --- /dev/null +++ b/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi @@ -0,0 +1,156 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Amlogic, Inc. All rights reserved. + */ + +#include +#include +#include +/ { + cpus:cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + core1 { + cpu = <&cpu1>; + }; + core2 { + cpu = <&cpu2>; + }; + core3 { + cpu = <&cpu3>; + }; + }; + cluster1 { + core0 { + cpu = <&cpu4>; + }; + core1 { + cpu = <&cpu5>; + }; + core2 { + cpu = <&cpu6>; + }; + core3 { + cpu = <&cpu7>; + }; + }; + }; + + cpu0:cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a73"; + reg = <0x0 0x0>; + enable-method = "psci"; + }; + + cpu1:cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a73"; + reg = <0x0 0x1>; + enable-method = "psci"; + }; + + cpu2:cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a73"; + reg = <0x0 0x2>; + enable-method = "psci"; + }; + + cpu3:cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a73"; + reg = <0x0 0x3>; + enable-method = "psci"; + }; + + cpu4:cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x100>; + enable-method = "psci"; + }; + + cpu5:cpu@101{ + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x101>; + enable-method = "psci"; + }; + + cpu6:cpu@102 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x102>; + enable-method = "psci"; + }; + + cpu7:cpu@103 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x103>; + enable-method = "psci"; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + xtal: xtal-clk { + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "xtal"; + #clock-cells = <0>; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gic: interrupt-controller@fff01000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x0 0xfff01000 0 0x1000>, + <0x0 0xfff02000 0 0x0100>; + interrupts = ; + }; + + apb4: bus@fe000000 { + compatible = "simple-bus"; + reg = <0x0 0xfe000000 0x0 0x480000>; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x480000>; + + uart_a: serial@78000 { + compatible = "amlogic,meson-s4-uart", + "amlogic,meson-ao-uart"; + reg = <0x0 0x78000 0x0 0x18>; + interrupts = ; + status = "disabled"; + clocks = <&xtal>,<&xtal>,<&xtal>; + clock-names = "xtal", "pclk", "baud"; + }; + }; + }; +};