| Message ID | 20230630083013.102334-9-alexghiti@rivosinc.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | riscv: Allow userspace to directly access perf counters | expand |
On Fri, Jun 30, 2023 at 10:30:11AM +0200, Alexandre Ghiti wrote: > riscv now uses this sysctl so document its usage for this architecture. > > Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com> > --- > Documentation/admin-guide/sysctl/kernel.rst | 26 +++++++++++++++++---- > 1 file changed, 22 insertions(+), 4 deletions(-) > > diff --git a/Documentation/admin-guide/sysctl/kernel.rst b/Documentation/admin-guide/sysctl/kernel.rst > index d85d90f5d000..c376692b372b 100644 > --- a/Documentation/admin-guide/sysctl/kernel.rst > +++ b/Documentation/admin-guide/sysctl/kernel.rst > @@ -941,16 +941,34 @@ enabled, otherwise writing to this file will return ``-EBUSY``. > The default value is 8. > > > -perf_user_access (arm64 only) > -================================= > +perf_user_access (arm64 and riscv only) > +======================================= > + > +Controls user space access for reading perf event counters. > > -Controls user space access for reading perf event counters. When set to 1, > -user space can read performance monitor counter registers directly. > +arm64 > +===== > > The default value is 0 (access disabled). Should add a blank line here. > +When set to 1, user space can read performance monitor counter registers > +directly. > > See Documentation/arm64/perf.rst for more information. > > +riscv > +===== > + > +When set to 0, user access is disabled. > + > +When set to 1, user space can read performance monitor counter registers > +directly only through perf, any direct access without perf intervention will Remove 'directly only' (It can't be both "direct" and "through" at the same time.) > +trigger an illegal instruction. > + > +The default value is 2, This is no longer true. > which enables legacy mode (user space has direct > +access to cycle and insret CSRs only). Note that this legacy value > +is deprecated and will be removed once all userspace applications are fixed. > + > +Note that the time CSR is for now always accessible to all modes. s/always accessible/always directly accessible/ Also, remove 'for now'. While we may change this in the future, I'm not sure if the 'for now' helps much. Maybe a "This may change in the future." type of sentence? Or, just nothing (for now :-) and we'll modify this document if it changes later. Thanks, drew > > pid_max > ======= > -- > 2.39.2 >
On Fri, Jun 30, 2023 at 1:16 PM Andrew Jones <ajones@ventanamicro.com> wrote: > > On Fri, Jun 30, 2023 at 10:30:11AM +0200, Alexandre Ghiti wrote: > > riscv now uses this sysctl so document its usage for this architecture. > > > > Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com> > > --- > > Documentation/admin-guide/sysctl/kernel.rst | 26 +++++++++++++++++---- > > 1 file changed, 22 insertions(+), 4 deletions(-) > > > > diff --git a/Documentation/admin-guide/sysctl/kernel.rst b/Documentation/admin-guide/sysctl/kernel.rst > > index d85d90f5d000..c376692b372b 100644 > > --- a/Documentation/admin-guide/sysctl/kernel.rst > > +++ b/Documentation/admin-guide/sysctl/kernel.rst > > @@ -941,16 +941,34 @@ enabled, otherwise writing to this file will return ``-EBUSY``. > > The default value is 8. > > > > > > -perf_user_access (arm64 only) > > -================================= > > +perf_user_access (arm64 and riscv only) > > +======================================= > > + > > +Controls user space access for reading perf event counters. > > > > -Controls user space access for reading perf event counters. When set to 1, > > -user space can read performance monitor counter registers directly. > > +arm64 > > +===== > > > > The default value is 0 (access disabled). > > Should add a blank line here. Done, thanks > > > +When set to 1, user space can read performance monitor counter registers > > +directly. > > > > See Documentation/arm64/perf.rst for more information. > > > > +riscv > > +===== > > + > > +When set to 0, user access is disabled. > > + > > +When set to 1, user space can read performance monitor counter registers > > +directly only through perf, any direct access without perf intervention will > > Remove 'directly only' > > (It can't be both "direct" and "through" at the same time.) > > > +trigger an illegal instruction. > > + > > +The default value is 2, > > This is no longer true. Damn, sorry about that. > > > which enables legacy mode (user space has direct > > +access to cycle and insret CSRs only). Note that this legacy value > > +is deprecated and will be removed once all userspace applications are fixed. > > + > > +Note that the time CSR is for now always accessible to all modes. > > s/always accessible/always directly accessible/ > > Also, remove 'for now'. While we may change this in the future, I'm not > sure if the 'for now' helps much. Maybe a "This may change in the future." > type of sentence? Or, just nothing (for now :-) and we'll modify this > document if it changes later. I won't say anything about the future, thanks! I also harmonized the "user space" and "userspace" in this document with what arm64 does. Thanks > > Thanks, > drew > > > > > pid_max > > ======= > > -- > > 2.39.2 > >
diff --git a/Documentation/admin-guide/sysctl/kernel.rst b/Documentation/admin-guide/sysctl/kernel.rst index d85d90f5d000..c376692b372b 100644 --- a/Documentation/admin-guide/sysctl/kernel.rst +++ b/Documentation/admin-guide/sysctl/kernel.rst @@ -941,16 +941,34 @@ enabled, otherwise writing to this file will return ``-EBUSY``. The default value is 8. -perf_user_access (arm64 only) -================================= +perf_user_access (arm64 and riscv only) +======================================= + +Controls user space access for reading perf event counters. -Controls user space access for reading perf event counters. When set to 1, -user space can read performance monitor counter registers directly. +arm64 +===== The default value is 0 (access disabled). +When set to 1, user space can read performance monitor counter registers +directly. See Documentation/arm64/perf.rst for more information. +riscv +===== + +When set to 0, user access is disabled. + +When set to 1, user space can read performance monitor counter registers +directly only through perf, any direct access without perf intervention will +trigger an illegal instruction. + +The default value is 2, which enables legacy mode (user space has direct +access to cycle and insret CSRs only). Note that this legacy value +is deprecated and will be removed once all userspace applications are fixed. + +Note that the time CSR is for now always accessible to all modes. pid_max =======
riscv now uses this sysctl so document its usage for this architecture. Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com> --- Documentation/admin-guide/sysctl/kernel.rst | 26 +++++++++++++++++---- 1 file changed, 22 insertions(+), 4 deletions(-)