diff mbox series

arm64: dts: imx8mn-var-som: add missing pull-up for onboard PHY reset pinmux

Message ID 20230704134800.204542-1-hugo@hugovil.com (mailing list archive)
State New, archived
Headers show
Series arm64: dts: imx8mn-var-som: add missing pull-up for onboard PHY reset pinmux | expand

Commit Message

Hugo Villeneuve July 4, 2023, 1:48 p.m. UTC 
From: Hugo Villeneuve <hvilleneuve@dimonoff.com>

For SOMs with an onboard PHY, the RESET_N pull-up resistor is
currently deactivated in the pinmux configuration. When the pinmux
code selects the GPIO function for this pin, with a default direction
of input, this prevents the RESET_N pin from being taken to the proper
3.3V level (deasserted), and this results in the PHY being not
detected since it is held in reset.

Taken from RESET_N pin description in ADIN13000 datasheet:
    This pin requires a 1K pull-up resistor to AVDD_3P3.

Activate the pull-up resistor to fix the issue.

Fixes: ade0176dd8a0 ("arm64: dts: imx8mn-var-som: Add Variscite VAR-SOM-MX8MN System on Module")
Signed-off-by: Hugo Villeneuve <hvilleneuve@dimonoff.com>
---
 arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Comments

Fabio Estevam July 4, 2023, 2:44 p.m. UTC | #1 
On Tue, Jul 4, 2023 at 10:48 AM Hugo Villeneuve <hugo@hugovil.com> wrote:
>
> From: Hugo Villeneuve <hvilleneuve@dimonoff.com>
>
> For SOMs with an onboard PHY, the RESET_N pull-up resistor is
> currently deactivated in the pinmux configuration. When the pinmux
> code selects the GPIO function for this pin, with a default direction
> of input, this prevents the RESET_N pin from being taken to the proper
> 3.3V level (deasserted), and this results in the PHY being not
> detected since it is held in reset.
>
> Taken from RESET_N pin description in ADIN13000 datasheet:
>     This pin requires a 1K pull-up resistor to AVDD_3P3.
>
> Activate the pull-up resistor to fix the issue.
>
> Fixes: ade0176dd8a0 ("arm64: dts: imx8mn-var-som: Add Variscite VAR-SOM-MX8MN System on Module")
> Signed-off-by: Hugo Villeneuve <hvilleneuve@dimonoff.com>

Reviewed-by: Fabio Estevam <festevam@gmail.com>
Shawn Guo July 18, 2023, 6:15 a.m. UTC | #2 
On Tue, Jul 04, 2023 at 09:48:00AM -0400, Hugo Villeneuve wrote:
> From: Hugo Villeneuve <hvilleneuve@dimonoff.com>
> 
> For SOMs with an onboard PHY, the RESET_N pull-up resistor is
> currently deactivated in the pinmux configuration. When the pinmux
> code selects the GPIO function for this pin, with a default direction
> of input, this prevents the RESET_N pin from being taken to the proper
> 3.3V level (deasserted), and this results in the PHY being not
> detected since it is held in reset.
> 
> Taken from RESET_N pin description in ADIN13000 datasheet:
>     This pin requires a 1K pull-up resistor to AVDD_3P3.
> 
> Activate the pull-up resistor to fix the issue.
> 
> Fixes: ade0176dd8a0 ("arm64: dts: imx8mn-var-som: Add Variscite VAR-SOM-MX8MN System on Module")
> Signed-off-by: Hugo Villeneuve <hvilleneuve@dimonoff.com>

Applied, thanks!
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi
index d3a67109d55b..b8946edf317b 100644
--- a/arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi
@@ -358,7 +358,7 @@  MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC		0x1f
 			MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC		0x91
 			MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91
 			MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f
-			MX8MN_IOMUXC_GPIO1_IO09_GPIO1_IO9		0x19
+			MX8MN_IOMUXC_GPIO1_IO09_GPIO1_IO9		0x159
 		>;
 	};