| Message ID | 20230705104815.511400-3-xu.yang_2@nxp.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [1/3] perf/imx_ddr: speed up overflow frequency of cycle counter | expand |
> > diff --git a/drivers/perf/fsl_imx8_ddr_perf.c > b/drivers/perf/fsl_imx8_ddr_perf.c > index 4e6cbfc48429..f7c832611713 100644 > --- a/drivers/perf/fsl_imx8_ddr_perf.c > +++ b/drivers/perf/fsl_imx8_ddr_perf.c > @@ -591,7 +591,9 @@ static void ddr_perf_pmu_enable(struct pmu *pmu) > struct ddr_pmu *ddr_pmu = to_ddr_pmu(pmu); > > /* enable cycle counter if cycle is not active event list */ > - if (ddr_pmu->events[EVENT_CYCLES_COUNTER] == NULL) > + if (ddr_pmu->events[EVENT_CYCLES_COUNTER] == NULL && EVENT_CYCLES_COUNTER is 0, if only enable cycles counter, below logic Will failure. Then counter will not work. > + (ddr_pmu->events[0] || ddr_pmu->events[1] || > + ddr_pmu->events[2] || ddr_pmu->events[3])) I suggest maintain a enabled_event counter, If(ddr_pmu->active_num==0) ddr_perf_counter_enable(..., true); ddr_pmu->active_num++; At disable function() { ddr_pmu->active_num --; if( ddr_pmu->active_num == 0) ddr_perf_counter_enable(.., false); } > ddr_perf_counter_enable(ddr_pmu, > EVENT_CYCLES_ID, > EVENT_CYCLES_COUNTER, > @@ -602,7 +604,9 @@ static void ddr_perf_pmu_disable(struct pmu *pmu) > { > struct ddr_pmu *ddr_pmu = to_ddr_pmu(pmu); > > - if (ddr_pmu->events[EVENT_CYCLES_COUNTER] == NULL) > + if (ddr_pmu->events[EVENT_CYCLES_COUNTER] == NULL && > + (ddr_pmu->events[0] || ddr_pmu->events[1] || > + ddr_pmu->events[2] || ddr_pmu->events[3])) > ddr_perf_counter_enable(ddr_pmu, > EVENT_CYCLES_ID, > EVENT_CYCLES_COUNTER, > -- > 2.34.1
Hi Frank, > -----Original Message----- > From: Frank Li <frank.li@nxp.com> > Sent: Wednesday, July 5, 2023 10:51 PM > To: Xu Yang <xu.yang_2@nxp.com> > Cc: will@kernel.org; mark.rutland@arm.com; shawnguo@kernel.org; s.hauer@pengutronix.de; kernel@pengutronix.de; > dl-linux-imx <linux-imx@nxp.com>; linux-arm-kernel@lists.infradead.org > Subject: RE: [PATCH 3/3] perf/imx_ddr: don't enable counter0 if none of 4 counters are used > > > > > diff --git a/drivers/perf/fsl_imx8_ddr_perf.c > > b/drivers/perf/fsl_imx8_ddr_perf.c > > index 4e6cbfc48429..f7c832611713 100644 > > --- a/drivers/perf/fsl_imx8_ddr_perf.c > > +++ b/drivers/perf/fsl_imx8_ddr_perf.c > > @@ -591,7 +591,9 @@ static void ddr_perf_pmu_enable(struct pmu *pmu) > > struct ddr_pmu *ddr_pmu = to_ddr_pmu(pmu); > > > > /* enable cycle counter if cycle is not active event list */ > > - if (ddr_pmu->events[EVENT_CYCLES_COUNTER] == NULL) > > + if (ddr_pmu->events[EVENT_CYCLES_COUNTER] == NULL && > > EVENT_CYCLES_COUNTER is 0, if only enable cycles counter, below logic > Will failure. Then counter will not work. Yes, cycle counter will not be enabled for counting at this point. However, cycle counter will be enabled after perf_pmu_enable() is called. My understanding is that ddr_perf_pmu_enable() is used to enable cycle counter when other counters is used for counting since other counters depends on cycle counter. > > > + (ddr_pmu->events[0] || ddr_pmu->events[1] || > > + ddr_pmu->events[2] || ddr_pmu->events[3])) > > I suggest maintain a enabled_event counter, > > If(ddr_pmu->active_num==0) > ddr_perf_counter_enable(..., true); > ddr_pmu->active_num++; > > At disable function() > { > ddr_pmu->active_num --; > if( ddr_pmu->active_num == 0) > ddr_perf_counter_enable(.., false); > } Will try to maintain a enabled_event counter. Thanks, Xu Yang > > > > ddr_perf_counter_enable(ddr_pmu, > > EVENT_CYCLES_ID, > > EVENT_CYCLES_COUNTER, > > @@ -602,7 +604,9 @@ static void ddr_perf_pmu_disable(struct pmu *pmu) > > { > > struct ddr_pmu *ddr_pmu = to_ddr_pmu(pmu); > > > > - if (ddr_pmu->events[EVENT_CYCLES_COUNTER] == NULL) > > + if (ddr_pmu->events[EVENT_CYCLES_COUNTER] == NULL && > > + (ddr_pmu->events[0] || ddr_pmu->events[1] || > > + ddr_pmu->events[2] || ddr_pmu->events[3])) > > ddr_perf_counter_enable(ddr_pmu, > > EVENT_CYCLES_ID, > > EVENT_CYCLES_COUNTER, > > -- > > 2.34.1
diff --git a/drivers/perf/fsl_imx8_ddr_perf.c b/drivers/perf/fsl_imx8_ddr_perf.c index 4e6cbfc48429..f7c832611713 100644 --- a/drivers/perf/fsl_imx8_ddr_perf.c +++ b/drivers/perf/fsl_imx8_ddr_perf.c @@ -591,7 +591,9 @@ static void ddr_perf_pmu_enable(struct pmu *pmu) struct ddr_pmu *ddr_pmu = to_ddr_pmu(pmu); /* enable cycle counter if cycle is not active event list */ - if (ddr_pmu->events[EVENT_CYCLES_COUNTER] == NULL) + if (ddr_pmu->events[EVENT_CYCLES_COUNTER] == NULL && + (ddr_pmu->events[0] || ddr_pmu->events[1] || + ddr_pmu->events[2] || ddr_pmu->events[3])) ddr_perf_counter_enable(ddr_pmu, EVENT_CYCLES_ID, EVENT_CYCLES_COUNTER, @@ -602,7 +604,9 @@ static void ddr_perf_pmu_disable(struct pmu *pmu) { struct ddr_pmu *ddr_pmu = to_ddr_pmu(pmu); - if (ddr_pmu->events[EVENT_CYCLES_COUNTER] == NULL) + if (ddr_pmu->events[EVENT_CYCLES_COUNTER] == NULL && + (ddr_pmu->events[0] || ddr_pmu->events[1] || + ddr_pmu->events[2] || ddr_pmu->events[3])) ddr_perf_counter_enable(ddr_pmu, EVENT_CYCLES_ID, EVENT_CYCLES_COUNTER,
In current driver, counter0 will be enabled after ddr_perf_pmu_enable() is called even though none of the 4 counters are used. This will cause counter0 continue to count until ddr_perf_pmu_disabled() is called. If pmu is not disabled all the time, the pmu interrupt will be asserted from time to time due to counter0 will overflow and irq handler will clear it. It's not an expected behavior. This patch will not enable counter0 if none of 4 counters are used. Fixes: 9a66d36cc7ac ("drivers/perf: imx_ddr: Add DDR performance counter support to perf") Signed-off-by: Xu Yang <xu.yang_2@nxp.com> --- drivers/perf/fsl_imx8_ddr_perf.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-)