From patchwork Fri Jul 7 05:33:31 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anshuman Khandual X-Patchwork-Id: 13304441 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BCE74EB64DA for ; Fri, 7 Jul 2023 05:34:31 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=8UFSYNdlr0b3fo5Kem9aCdQT/hpCOjGM8fFjyvlsGbI=; b=z/JXXC/hF5BeTi X8CtJtQW24zNx5o/HRR+KOYK+01ijVk8AmzURUlns4XPaylOWIqgsQ8pf7KHjHDgQTmV+O1Kp1tJs XFAEKk4H7DiQx67O7XMMAuKjxOmVB9RWmKWpjq60G++8V+Ym58eruQ/BDKOjQnbTvTF5/dJ3FHlRo Mg5fSjxC0nzzPeethP42H/Ly/PKrWoq6O9CVw28e7pzLE8WPoDqnf8mwFxoItachehDkQqPYQH+EV T84wTLlxJwdqFIaIKlc4XRngsi+hZGuPYYEMREVKjqrmRrXXdBXpkTraIxbUocRG06Y7pEeewxTbs 6EhkmX8CxA3gN3s0TDwQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qHe6b-003dEe-1A; Fri, 07 Jul 2023 05:34:09 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qHe6Y-003dD3-0X for linux-arm-kernel@lists.infradead.org; Fri, 07 Jul 2023 05:34:08 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id B029112FC; Thu, 6 Jul 2023 22:34:45 -0700 (PDT) Received: from a077893.arm.com (unknown [10.163.48.50]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 114983F740; Thu, 6 Jul 2023 22:33:59 -0700 (PDT) From: Anshuman Khandual To: linux-arm-kernel@lists.infradead.org Cc: Anshuman Khandual , Catalin Marinas , Will Deacon , Ryan Roberts , Mark Rutland , Andrew Morton , David Hildenbrand , Jonathan Corbet , linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org Subject: [RFC 4/4] docs: arm64: Add help document for pte dirty state management Date: Fri, 7 Jul 2023 11:03:31 +0530 Message-Id: <20230707053331.510041-5-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230707053331.510041-1-anshuman.khandual@arm.com> References: <20230707053331.510041-1-anshuman.khandual@arm.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230706_223406_299247_F0E65612 X-CRM114-Status: GOOD ( 18.75 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org PTE dirty state management is non-trivial on arm64 platform. This document explains how both software and hardware come together in correctly tracking PTE ditry state across various page table transactions. Cc: Catalin Marinas Cc: Will Deacon Cc: Jonathan Corbet Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Cc: linux-doc@vger.kernel.org Signed-off-by: Anshuman Khandual --- Documentation/arch/arm64/index.rst | 1 + Documentation/arch/arm64/pte-dirty.rst | 95 ++++++++++++++++++++++++++ 2 files changed, 96 insertions(+) create mode 100644 Documentation/arch/arm64/pte-dirty.rst diff --git a/Documentation/arch/arm64/index.rst b/Documentation/arch/arm64/index.rst index d08e924204bf..522f887f2a60 100644 --- a/Documentation/arch/arm64/index.rst +++ b/Documentation/arch/arm64/index.rst @@ -22,6 +22,7 @@ ARM64 Architecture perf pointer-authentication ptdump + pte-dirty silicon-errata sme sve diff --git a/Documentation/arch/arm64/pte-dirty.rst b/Documentation/arch/arm64/pte-dirty.rst new file mode 100644 index 000000000000..a6401696f6a3 --- /dev/null +++ b/Documentation/arch/arm64/pte-dirty.rst @@ -0,0 +1,95 @@ +.. SPDX-License-Identifier: GPL-2.0 +========================================= +Page Table Entry - Dirty State Management +========================================= + +1. Introduction +--------------- + +arm64 platform defines pte_dirty() to determine if the pte has been dirtied +i.e pte has been written info after the previous clean procedure. The dirty +state tracking could be achieved, either via software or hardware pte dirty +bit mechanism. On arm64 platform, pte_dirty() is implemented utilizing both +software and hardware dirty bits, making it non intuitive unlike many other +platforms. + +2. PTE Dirty Bits (SW and HW) +----------------------------- +Following are relevant PTE bit positions for dirty state tracking. + +- PTE_DIRTY is a software bit (55) in the PTE +- PTE_RDONLY is a hardware bit (7) in the PTE +- PTE_DBM is a hardware bit (51) in the PTE +- PTE_WRITE is a hardware bit (51) in the PTE - share position with PTE_DBM + +3. PTE Dirty State Tracking +--------------------------- +Without ARM64_HW_AFDBM enabled, PTE dirty state is tracked only in the SW. +PTE is marked read-only in HW, subsequent write access generates page fault +which can update the SW dirty bit and clear the read-only access in HW. + +With ARM64_HW_AFDBM enabled, PTE dirty state is tracked both in SW and HW. +PTE is marked read-only in HW while also enabling DBM tracking. Any write +access will clear the read-only bit while also preventing a page fault. As +PTE_DBM and PTE_WRITE share the same bit position, a dirty non-writable PTE +state cannot be tracked in hardware. This in turn necessitates dirty state +tracking (ARM64_HW_AFDBM enabled) to accommodate both software and hardware +PTE bits. This helps in avoiding a runtime check for ARM64_HW_AFDBM feature +being enabled on a given implementation. + +Testing and clearing PTE dirty state is relatively simple - + +#define pte_hw_dirty(pte) (pte_write(pte) && !pte_rdonly(pte)) +#define pte_sw_dirty(pte) (!!(pte_val(pte) & PTE_DIRTY)) +#define pte_dirty(pte) (pte_sw_dirty(pte) || pte_hw_dirty(pte)) + +static inline pte_t pte_mkclean(pte_t pte) +{ + /* + * Subsequent call to pte_hw_clr_dirty() is not required + * because pte_sw_clr_dirty() in turn does that as well. + */ + return pte_sw_clr_dirty(pte); +} + +But marking a dirty state, creating a write protected entry etc now becomes +bit non-trivial in hardware. as PTE_RDONLY bit could only be cleared if the +write bit is also set. + +static inline pte_t pte_hw_mkdirty(pte_t pte) +{ + if (pte_write(pte)) + return clear_pte_bit(pte, __pgprot(PTE_RDONLY)); + + return pte; +} + +Hence marking a dirty state triggers marking both SW and HW dirty bits, so +that if the HW suppoprt is unavailable or insufficient (dirty non-writable) +, SW mechanism would still put it in a dirty state. + +static inline pte_t pte_mkdirty(pte_t pte) +{ + pte = pte_sw_mkdirty(pte); + pte = pte_hw_mkdirty(pte); + return pte; +} + +4. Preserving PTE HW Dirty State +-------------------------------- +If for some reason HW dirty bits (PTE_WRITE, PTE_RDONLY) need to be cleared +the dirty state must be transferred as SW dirty bit ensuring persistence of +the dirty state across the operation. + +static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) +{ + ..... + pte = pte_preserve_hw_dirty(pte_t pte); + ..... +} + +static inline pte_t pte_wrprotect(pte_t pte) +{ + pte = pte_preserve_hw_dirty(pte_t pte); + ..... +}