From patchwork Fri Jul 21 20:37:47 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Duje_Mihanovi=C4=87?= X-Patchwork-Id: 13322545 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3EEC5C001DE for ; Fri, 21 Jul 2023 21:06:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=4NlgaLOc5Oaur5l71r/XFVNIjO4vj9IuGOBWaZlJiEs=; b=UvtDrWdk6AjfDx 0QNMrsp0h2RL9D/A9lYi/KpM81fqnFitIlf5e5W6LkCXO5Ytfuf4A0Ka2v0cA5cN6EmKGcVJWcTDh FMm2G3Zyc+hlsd3DJcXdpCp/IAFrxxGppOQuOcw3+jv83wGVglnL4MMwNAFWcXwzRTz4Dmg83ATNf l50FZ+m889nunr6EuGMcFPDwRWK/90Wf6sJJULiQzE2s7+f5BAj48qgCsLQosZzuNLUlCz1Vsfmak Wu54OaRrdJosgf9e12Szwzmy/umU0tZChWiDaPYTxk8MERJhxWszhCgx6hu1qzjbmsGBAXsWHhqUC 8wrtcIl8lqABu4jmS70A==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qMxKb-00F7UE-0i; Fri, 21 Jul 2023 21:06:33 +0000 Received: from mx1.hosting.skole.hr ([161.53.165.185] helo=mx.skole.hr) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1qMxKL-00F7Or-2Y for linux-arm-kernel@lists.infradead.org; Fri, 21 Jul 2023 21:06:20 +0000 Received: from mx1.hosting.skole.hr (localhost.localdomain [127.0.0.1]) by mx.skole.hr (mx.skole.hr) with ESMTP id D31C586D1D; Fri, 21 Jul 2023 23:06:12 +0200 (CEST) From: =?utf-8?q?Duje_Mihanovi=C4=87?= To: =?utf-8?q?Duje_Mihanovi=C4=87?= , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, afaerber@suse.com Subject: [PATCH 05/10] dt-bindings: clock: Add Marvell PXA1908 clock bindings Date: Fri, 21 Jul 2023 22:37:47 +0200 Message-ID: <20230721210042.21535-6-duje.mihanovic@skole.hr> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230721210042.21535-1-duje.mihanovic@skole.hr> References: <20230721210042.21535-1-duje.mihanovic@skole.hr> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230721_140617_992445_3B0CFC28 X-CRM114-Status: GOOD ( 10.50 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add the dt bindings for Marvell PXA1908 clock controller. Signed-off-by: Duje Mihanović --- include/dt-bindings/clock/marvell,pxa1908.h | 93 +++++++++++++++++++++ 1 file changed, 93 insertions(+) create mode 100644 include/dt-bindings/clock/marvell,pxa1908.h diff --git a/include/dt-bindings/clock/marvell,pxa1908.h b/include/dt-bindings/clock/marvell,pxa1908.h new file mode 100644 index 000000000000..da9c5d499ae4 --- /dev/null +++ b/include/dt-bindings/clock/marvell,pxa1908.h @@ -0,0 +1,93 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#ifndef __DTS_MARVELL_PXA1908_CLOCK_H +#define __DTS_MARVELL_PXA1908_CLOCK_H + +/* plls */ +#define PXA1908_CLK_CLK32 0x1 +#define PXA1908_CLK_VCTCXO 0x2 +#define PXA1908_CLK_PLL1_624 0x3 +#define PXA1908_CLK_PLL1_416 0x4 +#define PXA1908_CLK_PLL1_499 0x5 +#define PXA1908_CLK_PLL1_832 0x6 +#define PXA1908_CLK_PLL1_1248 0x7 +#define PXA1908_CLK_PLL1_D2 0x8 +#define PXA1908_CLK_PLL1_D4 0x9 +#define PXA1908_CLK_PLL1_D8 0xa +#define PXA1908_CLK_PLL1_D16 0xb +#define PXA1908_CLK_PLL1_D6 0xc +#define PXA1908_CLK_PLL1_D12 0xd +#define PXA1908_CLK_PLL1_D24 0xe +#define PXA1908_CLK_PLL1_D48 0xf +#define PXA1908_CLK_PLL1_D96 0x10 +#define PXA1908_CLK_PLL1_D13 0x11 +#define PXA1908_CLK_PLL1_32 0x12 +#define PXA1908_CLK_PLL1_208 0x13 +#define PXA1908_CLK_PLL1_117 0x14 +#define PXA1908_CLK_PLL1_416_GATE 0x15 +#define PXA1908_CLK_PLL1_624_GATE 0x16 +#define PXA1908_CLK_PLL1_832_GATE 0x17 +#define PXA1908_CLK_PLL1_1248_GATE 0x18 +#define PXA1908_CLK_PLL1_D2_GATE 0x19 +#define PXA1908_CLK_PLL1_499_EN 0x1a +#define PXA1908_CLK_PLL2VCO 0x1b +#define PXA1908_CLK_PLL2 0x1c +#define PXA1908_CLK_PLL2P 0x1d +#define PXA1908_CLK_PLL2VCODIV3 0x1e +#define PXA1908_CLK_PLL3VCO 0x1f +#define PXA1908_CLK_PLL3 0x20 +#define PXA1908_CLK_PLL3P 0x21 +#define PXA1908_CLK_PLL3VCODIV3 0x22 +#define PXA1908_CLK_PLL4VCO 0x23 +#define PXA1908_CLK_PLL4 0x24 +#define PXA1908_CLK_PLL4P 0x25 +#define PXA1908_CLK_PLL4VCODIV3 0x26 +#define PXA1908_MPMU_NR_CLKS 38 + +/* apb (apbc) peripherals */ +#define PXA1908_CLK_UART0 0x1 +#define PXA1908_CLK_UART1 0x2 +#define PXA1908_CLK_GPIO 0x3 +#define PXA1908_CLK_PWM0 0x4 +#define PXA1908_CLK_PWM1 0x5 +#define PXA1908_CLK_PWM2 0x6 +#define PXA1908_CLK_PWM3 0x7 +#define PXA1908_CLK_SSP0 0x8 +#define PXA1908_CLK_SSP1 0x9 +#define PXA1908_CLK_IPC_RST 0xa +#define PXA1908_CLK_RTC 0xb +#define PXA1908_CLK_TWSI0 0xc +#define PXA1908_CLK_KPC 0xd +#define PXA1908_CLK_SWJTAG 0x11 +#define PXA1908_CLK_SSP2 0x14 +#define PXA1908_CLK_TWSI1 0x19 +#define PXA1908_CLK_THERMAL 0x1c +#define PXA1908_CLK_TWSI3 0x1d +#define PXA1908_APBC_NR_CLKS 0x30 + +/* apb (apbcp) peripherals */ +#define PXA1908_CLK_UART2 0x7 +#define PXA1908_CLK_TWSI2 0xa +#define PXA1908_CLK_AICER 0xe +#define PXA1908_APBCP_NR_CLKS 0xe + +/* axi (apmu) peripherals */ +#define PXA1908_CLK_CCIC1 0x9 +#define PXA1908_CLK_ISP 0xe +#define PXA1908_CLK_GATE_CTRL 0x10 +#define PXA1908_CLK_DSI1 0x11 +#define PXA1908_CLK_DISP1 0x13 +#define PXA1908_CLK_CCIC0 0x14 +#define PXA1908_CLK_SDH0 0x15 +#define PXA1908_CLK_SDH1 0x16 +#define PXA1908_CLK_SDH2 0x38 +#define PXA1908_CLK_USB 0x17 +#define PXA1908_CLK_NF 0x18 +#define PXA1908_CLK_CORE_DEBUG 0x24 +#define PXA1908_CLK_VPU 0x29 +#define PXA1908_CLK_GC 0x51 +#define PXA1908_CLK_GC2D 0x3d +#define PXA1908_CLK_TRACE 0x42 +#define PXA1908_CLK_DVC_DFC_DEBUG 0x50 +#define PXA1908_APMU_NR_CLKS 0x60 + +#endif