diff mbox series

[11/14] ARM: dts: rockchip: rv1126: Add MIPI DSI pipeline

Message ID 20230731110012.2913742-12-jagan@edgeble.ai (mailing list archive)
State New, archived
Headers show
Series drm: rockchip: Add RV1126 Display (MIPI DSI) support | expand

Commit Message

Jagan Teki July 31, 2023, 11 a.m. UTC
MIPI DSI controller in RV1126 has integrated MIPI D-PHY V1.2
thatĀ supports up to 4 lanes with a 4Gbps transfer rate.

Add MIPI DSI pipeline for Rockchip RV1126.

Signed-off-by: Jagan Teki <jagan@edgeble.ai>
---
Cc: devicetree@vger.kernel.org
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
Cc: Conor Dooley <conor+dt@kernel.org>

 arch/arm/boot/dts/rockchip/rv1126.dtsi | 49 ++++++++++++++++++++++++++
 1 file changed, 49 insertions(+)
diff mbox series

Patch

diff --git a/arch/arm/boot/dts/rockchip/rv1126.dtsi b/arch/arm/boot/dts/rockchip/rv1126.dtsi
index 9ccd1bad6229..512cc18762b6 100644
--- a/arch/arm/boot/dts/rockchip/rv1126.dtsi
+++ b/arch/arm/boot/dts/rockchip/rv1126.dtsi
@@ -276,6 +276,20 @@  cru: clock-controller@ff490000 {
 		#reset-cells = <1>;
 	};
 
+	dsi_dphy: mipi-dphy@ff4d0000 {
+		compatible = "rockchip,rv1126-dsi-dphy";
+		reg = <0xff4d0000 0x500>;
+		assigned-clocks = <&pmucru CLK_MIPIDSIPHY_REF>;
+		assigned-clock-rates = <24000000>;
+		clock-names = "ref", "pclk";
+		clocks = <&pmucru CLK_MIPIDSIPHY_REF>, <&cru PCLK_DSIPHY>;
+		#phy-cells = <0>;
+		power-domains = <&power RV1126_PD_VO>;
+		reset-names = "apb";
+		resets = <&cru SRST_DSIPHY_P>;
+		status = "disabled";
+	};
+
 	dmac: dma-controller@ff4e0000 {
 		compatible = "arm,pl330", "arm,primecell";
 		reg = <0xff4e0000 0x4000>;
@@ -420,6 +434,7 @@  vop_out_rgb: endpoint@0 {
 
 			vop_out_dsi: endpoint@1 {
 				reg = <1>;
+				remote-endpoint = <&dsi_in_vop>;
 			};
 		};
 	};
@@ -435,6 +450,40 @@  vop_mmu: iommu@ffb00f00 {
 		status = "disabled";
 	};
 
+	dsi: dsi@ffb30000 {
+		compatible = "rockchip,rv1126-mipi-dsi", "snps,dw-mipi-dsi";
+		reg = <0xffb30000 0x500>;
+		interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
+		clock-names = "pclk";
+		clocks = <&cru PCLK_DSIHOST>;
+		phy-names = "dphy";
+		phys = <&dsi_dphy>;
+		power-domains = <&power RV1126_PD_VO>;
+		reset-names = "apb";
+		resets = <&cru SRST_DSIHOST_P>;
+		rockchip,grf = <&grf>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+
+				dsi_in_vop: endpoint {
+					remote-endpoint = <&vop_out_dsi>;
+				};
+			};
+
+			port@1 {
+				reg = <1>;
+			};
+		};
+	};
+
 	gmac: ethernet@ffc40000 {
 		compatible = "rockchip,rv1126-gmac", "snps,dwmac-4.20a";
 		reg = <0xffc40000 0x4000>;