From patchwork Mon Jul 31 10:48:14 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Shavit X-Patchwork-Id: 13334295 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 69C25C001DE for ; Mon, 31 Jul 2023 10:49:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:From:Subject:Message-ID: References:Mime-Version:In-Reply-To:Date:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=MkKmiHCDI1Os+Inf1kLZhpcFXD23g3vruEamjvX9lv0=; b=YHXlHPPokbYX7ATLnyarNq+5JA f3XeGGzAoxfYAdBDdCR92Q3YdXM4V6q3QJwTBaZ+zPDGtQOHQcI4eLKyCx3eNBlSAXUzI0ZpDRXCp TDHl4hc3D30PhU0EJGuRvG0vAsa0XGciMFH8P9kf8ANMkVMvkQyjqXji8b/b7Ujhpy/CWx98JHSdF 2yf4EgN1P7HVeUuwTFWgqkHpIWYR1EFqbycAgqaZkU2ALiUAUPBK/bNOxTbK4IckGGrhFKMm+YqzB fb6GKbYQ8GQrxQCLQTQ/CxNtX3E+BuhN2JgGe1x/Oomauu+7Xi2Ad3iVYv6kbOSUv1WA6h3Vua3F4 sASXmaNQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qQQSi-00F9Ob-0v; Mon, 31 Jul 2023 10:49:16 +0000 Received: from mail-yw1-x1149.google.com ([2607:f8b0:4864:20::1149]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1qQQST-00F9GD-2d for linux-arm-kernel@lists.infradead.org; Mon, 31 Jul 2023 10:49:03 +0000 Received: by mail-yw1-x1149.google.com with SMTP id 00721157ae682-583c49018c6so51273537b3.0 for ; Mon, 31 Jul 2023 03:49:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20221208; t=1690800540; x=1691405340; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=5wCGxdM3vMHiwD5Hqt1d7Th7Pi/IDzxiPCnlsNf6ST4=; b=wvipL4WYLuG06Yh5YopeGwe+XP+zY71R/EbIkI2asNYrYY+npiquOLOKtTV2H4wE2V EaHCyurHW1OnBNBicb3akuqlgF4MJPoQognV8Zlk2nlY3F68isgainEajrK0YmO8BFKX v9uxGx2aUalsMGIWmLEXx77Qt9MTtXIWfIaXsQN9QhUdFKcBkreF2WgktcFBR6IE/uoH 55LrshvxNW8mBQlz05AGY0+XgdTfXjNZFqKztaF2CceW22NfA18nxf+yKVrkIKH/GwA+ awt3aG+Mo/+5YJJba+ZkC4K6v8Jqe+YiictB/4pRzc9kXU9nN1RKGk/pvbOiCaLhUeE+ mn5A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1690800540; x=1691405340; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=5wCGxdM3vMHiwD5Hqt1d7Th7Pi/IDzxiPCnlsNf6ST4=; b=D3rsQwe/uvmfGi4+8DqmGCxo166LS7lJ++bMLrI8ClYVkY/bH/LMhwTJIXhwKNgAHj Dq2/HubfMKjugLjNkKv++q3yShh6f/mMEb/NNxbOs4qqAWgr2jGQV8TiKzQPLkNa+ax1 Ho1I4dBs7zhbrSTtg2tofCtYCe1NrKHh4ERQvA8nym3H7C7m0IBcvXofIGWYgNKu65b+ BlC1UbD/IV91ezEkfrJ9bIlH627GiadpsUqXwASiWEILBUb+XlobEdOjgmevb8ckyAFf eU8g1qu230mncf6fi/x2Iay7PPFpuTOQSy8vjz2SqkDyzmXW4TFCbtoTt6B1BW+nw+HQ iL9g== X-Gm-Message-State: ABy/qLaYA/7RoLBBGOTGgwL1bZDXPVNSym3K4PCzDFRx6ywhFzw903RK Pbf7DLRSI25lt75b3YYmx410dvBhy3ED X-Google-Smtp-Source: APBJJlFQ7Qm2AbHHFTv+59ukHyucVUan8ZyEh930iZGIBXi3F+1k6wJAPucN7Z8mtOU9tmxewSWQWBEKDQ12 X-Received: from mshavit.ntc.corp.google.com ([2401:fa00:95:20c:affc:ad1d:5cbb:3c6a]) (user=mshavit job=sendgmr) by 2002:a25:7341:0:b0:d0b:ca14:33fd with SMTP id o62-20020a257341000000b00d0bca1433fdmr49423ybc.8.1690800540379; Mon, 31 Jul 2023 03:49:00 -0700 (PDT) Date: Mon, 31 Jul 2023 18:48:14 +0800 In-Reply-To: <20230731104833.800114-1-mshavit@google.com> Mime-Version: 1.0 References: <20230731104833.800114-1-mshavit@google.com> X-Mailer: git-send-email 2.41.0.585.gd2178a4bd4-goog Message-ID: <20230731184817.v2.4.I5aa89c849228794a64146cfe86df21fb71629384@changeid> Subject: [PATCH v2 4/8] iommu/arm-smmu-v3: move stall_enabled to the cd table From: Michael Shavit To: iommu@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: will@kernel.org, robin.murphy@arm.com, nicolinc@nvidia.com, jgg@nvidia.com, jean-philippe@linaro.org, Michael Shavit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230731_034901_852956_D6C4BB8F X-CRM114-Status: GOOD ( 18.29 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org This controls whether CD entries will have the stall bit set when writing entries into the table. Signed-off-by: Michael Shavit Reviewed-by: Jason Gunthorpe --- Changes in v2: - Use a bitfield instead of a bool for stall_enabled drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 8 ++++---- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 3 ++- 2 files changed, 6 insertions(+), 5 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index 8a286e3838d70..654acf6002bf3 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -1114,7 +1114,7 @@ int arm_smmu_write_ctx_desc(struct arm_smmu_domain *smmu_domain, int ssid, FIELD_PREP(CTXDESC_CD_0_ASID, cd->asid) | CTXDESC_CD_0_V; - if (smmu_domain->stall_enabled) + if (smmu_domain->cd_table.stall_enabled) val |= CTXDESC_CD_0_S; } @@ -1141,6 +1141,7 @@ static int arm_smmu_alloc_cd_tables(struct arm_smmu_domain *smmu_domain, struct arm_smmu_device *smmu = smmu_domain->smmu; struct arm_smmu_ctx_desc_cfg *cdcfg = &smmu_domain->cd_table; + cdcfg->stall_enabled = master->stall_enabled; cdcfg->max_cds_bits = master->ssid_bits; max_contexts = 1 << cdcfg->max_cds_bits; @@ -2121,8 +2122,6 @@ static int arm_smmu_domain_finalise_s1(struct arm_smmu_domain *smmu_domain, if (ret) goto out_unlock; - smmu_domain->stall_enabled = master->stall_enabled; - ret = arm_smmu_alloc_cd_tables(smmu_domain, master); if (ret) goto out_free_asid; @@ -2461,7 +2460,8 @@ static int arm_smmu_attach_dev(struct iommu_domain *domain, struct device *dev) ret = -EINVAL; goto out_unlock; } else if (smmu_domain->stage == ARM_SMMU_DOMAIN_S1 && - smmu_domain->stall_enabled != master->stall_enabled) { + smmu_domain->cd_table.stall_enabled != + master->stall_enabled) { ret = -EINVAL; goto out_unlock; } diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h index 35a93e8858872..05b1f0ee60808 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -597,6 +597,8 @@ struct arm_smmu_ctx_desc_cfg { unsigned int num_l1_ents; /* log2 of the maximum number of CDs supported by this table */ u8 max_cds_bits; + /* Whether CD entries in this table have the stall bit set. */ + u8 stall_enabled:1; }; struct arm_smmu_s2_cfg { @@ -714,7 +716,6 @@ struct arm_smmu_domain { struct mutex init_mutex; /* Protects smmu pointer */ struct io_pgtable_ops *pgtbl_ops; - bool stall_enabled; atomic_t nr_ats_masters; enum arm_smmu_domain_stage stage;