From patchwork Tue Aug 1 15:20:04 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jing Zhang X-Patchwork-Id: 13336937 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id F3FE1C001DF for ; Tue, 1 Aug 2023 15:21:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:From:Subject:Message-ID: References:Mime-Version:In-Reply-To:Date:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=y5fWThw6EFPjSsTJVWV7OPmfi3L5YywtbqU8nBoVfd8=; b=NccuhzcmgkVIg8EcshlgKzdWIT EvOhRmEKslVoTCaNSbXwUrdZfTq4C0RnFYiDahUvKxgxY612tRz/a1AwBsJF6sjdOR+lRIhGpx/cl sUVe39xEQQKA9BlqVFsknygb5a6+Ou+RBgw7oNb3NxU5ywoXuQreXr2Cp6AWgnNEkCfYWTGcxvbYO YDJEfziG925Gspc/Rgj3qtAnknh6hEvYyFMAQmB6WVBAkd5ASal3QCk6ULvAhtfQB491DeYZ7u7ac EOeMBre4DldcI0CbiYeC7tVYEDa3VfXzqE1WP+7gQGvMIyeyRsYl3Z35YSHU5ohtSL2IDeWWyjDPb 62etvYlw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qQrAr-002hme-27; Tue, 01 Aug 2023 15:20:37 +0000 Received: from mail-yw1-x114a.google.com ([2607:f8b0:4864:20::114a]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1qQrAl-002hf3-2V for linux-arm-kernel@lists.infradead.org; Tue, 01 Aug 2023 15:20:33 +0000 Received: by mail-yw1-x114a.google.com with SMTP id 00721157ae682-57320c10635so67950597b3.3 for ; Tue, 01 Aug 2023 08:20:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20221208; t=1690903227; x=1691508027; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=qCRHZVqddoTSJorH44HmZhNcqs8I6hBKdRtCxXPKdcc=; b=xUk8/PBRR9uYT5FnKEA4Cve1KEBIbakV95yHK6lLIe0Jd2hkciskQ+1vWIYAFyfZsZ SCkb2hADUdQOJtA//rrCMnQqJxn7PZYTyBKgjUvlcLWBDivD0rNSjH0Fm+S/uMyIEuFs VzbTvhXsMlyB9/+mbWNZqt/86Gv1Xe0g33EdLC7mJnLLcnPFZy2nXLx+saOoj4JLpNhp AMystXt2IFjzAh++Dg3UFla/zhMzyRxWd4Wa7p/+SCvTajnY3eXp8FLVkLfDFKQftdIM g4DDq5Zt3PVmyqublIcK+lJiF1+3ve287QP9AsxsxDSKfxLiQ3KOQdv+rISsCFsQKj12 OBeA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1690903227; x=1691508027; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=qCRHZVqddoTSJorH44HmZhNcqs8I6hBKdRtCxXPKdcc=; b=A/2mC4sixhr1v9d0PhCKkRpQJ+YI2axbrP7cSBI9AAYICiDvphaULM/u2iMAv3Eqf4 f0LGrx7BAXXxiFweuujna8x5rqkf71ryjqCOyljSiqaxyIqPK2VcgTbOIOG6cmoUGp/K oto19a9Lp8pB51cIxCgepffEb0RMv2WfGDrW3BtQyErsPPPLZfQk2qKTrfOPDws/A0Ay UqSSEa+WVpDcR71vURRe0PixQgfQpomMOc8APhT0b2+e7SbE3snoJXL90v2UndmYTl2t JDLdp3yJAIHLCyYwYsNskOmTWK0qSy9nehziLLWx2RPfAcsN+DA10xSTyni5O7VvPmy1 goNw== X-Gm-Message-State: ABy/qLYRlBizwfV8p9BPTN+4CQaFkdVN7vIahYFwTsu/ZUBy1SH88LWJ Cav072ECZuBNHb/sCdqdmO8BSlGLxxCiFul7WA== X-Google-Smtp-Source: APBJJlEnpgyitr9PUTByZOiYn2bZXCXM8oRbrFOt19UqT5CZCMNf1UqGqdwhB7FXBYLGi3iq9DArG2kfHOXto4DNyA== X-Received: from jgzg.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:1acf]) (user=jingzhangos job=sendgmr) by 2002:a25:ab86:0:b0:d0d:a7bc:4040 with SMTP id v6-20020a25ab86000000b00d0da7bc4040mr92863ybi.0.1690903227620; Tue, 01 Aug 2023 08:20:27 -0700 (PDT) Date: Tue, 1 Aug 2023 08:20:04 -0700 In-Reply-To: <20230801152007.337272-1-jingzhangos@google.com> Mime-Version: 1.0 References: <20230801152007.337272-1-jingzhangos@google.com> X-Mailer: git-send-email 2.41.0.585.gd2178a4bd4-goog Message-ID: <20230801152007.337272-9-jingzhangos@google.com> Subject: [PATCH v7 08/10] KVM: arm64: Refactor helper Macros for idreg desc From: Jing Zhang To: KVM , KVMARM , ARMLinux , Marc Zyngier , Oliver Upton Cc: Will Deacon , Paolo Bonzini , James Morse , Alexandru Elisei , Suzuki K Poulose , Fuad Tabba , Reiji Watanabe , Raghavendra Rao Ananta , Suraj Jitindar Singh , Cornelia Huck , Jing Zhang X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230801_082031_815920_18AD09E3 X-CRM114-Status: GOOD ( 14.03 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add some helpers to ease the declaration for idreg desc. These Macros will be heavily used for future commits enabling writable for idregs. Signed-off-by: Jing Zhang --- arch/arm64/kvm/sys_regs.c | 79 ++++++++++++++++----------------------- 1 file changed, 33 insertions(+), 46 deletions(-) diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 0a406058abb9..9ca23cfec9e5 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -1844,27 +1844,37 @@ static unsigned int elx2_visibility(const struct kvm_vcpu *vcpu, * from userspace. */ -/* sys_reg_desc initialiser for known cpufeature ID registers */ -#define ID_SANITISED(name) { \ - SYS_DESC(SYS_##name), \ - .access = access_id_reg, \ - .get_user = get_id_reg, \ - .set_user = set_id_reg, \ - .visibility = id_visibility, \ - .reset = kvm_read_sanitised_id_reg, \ - .val = 0, \ +#define ID_DESC(name, _set_user, _visibility, _reset, mask) { \ + SYS_DESC(SYS_##name), \ + .access = access_id_reg, \ + .get_user = get_id_reg, \ + .set_user = _set_user, \ + .visibility = _visibility, \ + .reset = _reset, \ + .val = mask, \ } /* sys_reg_desc initialiser for known cpufeature ID registers */ -#define AA32_ID_SANITISED(name) { \ - SYS_DESC(SYS_##name), \ - .access = access_id_reg, \ - .get_user = get_id_reg, \ - .set_user = set_id_reg, \ - .visibility = aa32_id_visibility, \ - .reset = kvm_read_sanitised_id_reg, \ - .val = 0, \ -} +#define _ID_SANITISED(name, _set_user, _reset) \ + ID_DESC(name, _set_user, id_visibility, _reset, 0) +#define ID_SANITISED(name) \ + _ID_SANITISED(name, set_id_reg, kvm_read_sanitised_id_reg) + +#define _ID_SANITISED_W(name, _set_user, _reset) \ + ID_DESC(name, _set_user, id_visibility, _reset, GENMASK(63, 0)) +#define ID_SANITISED_W(name) \ + _ID_SANITISED_W(name, set_id_reg, kvm_read_sanitised_id_reg) + +/* sys_reg_desc initialiser for known cpufeature ID registers */ +#define _AA32_ID_SANITISED(name, _set_user, _reset) \ + ID_DESC(name, _set_user, aa32_id_visibility, _reset, 0) +#define AA32_ID_SANITISED(name) \ + _AA32_ID_SANITISED(name, set_id_reg, kvm_read_sanitised_id_reg) + +#define _AA32_ID_SANITISED_W(name, _set_user, _reset) \ + ID_DESC(name, _set_user, aa32_id_visibility, _reset, GENMASK(63, 0)) +#define AA32_ID_SANITISED_W(name) \ + _AA32_ID_SANITISED_W(name, set_id_reg, kvm_read_sanitised_id_reg) /* * sys_reg_desc initialiser for architecturally unallocated cpufeature ID @@ -1886,15 +1896,8 @@ static unsigned int elx2_visibility(const struct kvm_vcpu *vcpu, * For now, these are exposed just like unallocated ID regs: they appear * RAZ for the guest. */ -#define ID_HIDDEN(name) { \ - SYS_DESC(SYS_##name), \ - .access = access_id_reg, \ - .get_user = get_id_reg, \ - .set_user = set_id_reg, \ - .visibility = raz_visibility, \ - .reset = kvm_read_sanitised_id_reg, \ - .val = 0, \ -} +#define ID_HIDDEN(name) \ + ID_DESC(name, set_id_reg, raz_visibility, kvm_read_sanitised_id_reg, 0) static bool access_sp_el1(struct kvm_vcpu *vcpu, struct sys_reg_params *p, @@ -2001,13 +2004,7 @@ static const struct sys_reg_desc sys_reg_descs[] = { /* CRm=1 */ AA32_ID_SANITISED(ID_PFR0_EL1), AA32_ID_SANITISED(ID_PFR1_EL1), - { SYS_DESC(SYS_ID_DFR0_EL1), - .access = access_id_reg, - .get_user = get_id_reg, - .set_user = set_id_dfr0_el1, - .visibility = aa32_id_visibility, - .reset = read_sanitised_id_dfr0_el1, - .val = GENMASK(63, 0), }, + _AA32_ID_SANITISED_W(ID_DFR0_EL1, set_id_dfr0_el1, read_sanitised_id_dfr0_el1), ID_HIDDEN(ID_AFR0_EL1), AA32_ID_SANITISED(ID_MMFR0_EL1), AA32_ID_SANITISED(ID_MMFR1_EL1), @@ -2036,12 +2033,7 @@ static const struct sys_reg_desc sys_reg_descs[] = { /* AArch64 ID registers */ /* CRm=4 */ - { SYS_DESC(SYS_ID_AA64PFR0_EL1), - .access = access_id_reg, - .get_user = get_id_reg, - .set_user = set_id_reg, - .reset = read_sanitised_id_aa64pfr0_el1, - .val = GENMASK(63, 0), }, + _ID_SANITISED_W(ID_AA64PFR0_EL1, set_id_reg, read_sanitised_id_aa64pfr0_el1), ID_SANITISED(ID_AA64PFR1_EL1), ID_UNALLOCATED(4,2), ID_UNALLOCATED(4,3), @@ -2051,12 +2043,7 @@ static const struct sys_reg_desc sys_reg_descs[] = { ID_UNALLOCATED(4,7), /* CRm=5 */ - { SYS_DESC(SYS_ID_AA64DFR0_EL1), - .access = access_id_reg, - .get_user = get_id_reg, - .set_user = set_id_aa64dfr0_el1, - .reset = read_sanitised_id_aa64dfr0_el1, - .val = GENMASK(63, 0), }, + _ID_SANITISED_W(ID_AA64DFR0_EL1, set_id_aa64dfr0_el1, read_sanitised_id_aa64dfr0_el1), ID_SANITISED(ID_AA64DFR1_EL1), ID_UNALLOCATED(5,2), ID_UNALLOCATED(5,3),