From patchwork Tue Aug 1 18:35:21 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Shavit X-Patchwork-Id: 13337161 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E5E16C0015E for ; Tue, 1 Aug 2023 18:39:34 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:From:Subject:Message-ID: References:Mime-Version:In-Reply-To:Date:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=dLfdKGW7WOMBTSOKAZetXe87r/mesQ3H82hJPKobspo=; b=veAeK6HJUhd3PlcNQylavFwPFv 60WbEGyGbibRiI0gNJWHzZo0hjz7nP7DwqszONoMpmlp7MCEPBlIgL4vyrXCjvmQNSj2IWtUG2wba pRjkp/rGbwfVqOKR0HsP1HbOmekUrc1k3bSMCypnxrp1guC7DvLWeIt8nlZNM9LpL1GhreY2vFosh N8T/ycCdAaZqprbJTyc8Ew3ryMWjrtTNOnKQ7p4w+fYtlydY82yJk6svz9U/t/cv1FqtHueLabJOY PAVCqtpG/n1AmLM1Dvs77eUhkULZGIEzbUtXGG4Ir8RIOrf28GJZ1evPqxLh1ICzJ4VlYcv8k3RMR ApHYomhQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qQuH5-0032vI-1d; Tue, 01 Aug 2023 18:39:15 +0000 Received: from mail-yb1-xb49.google.com ([2607:f8b0:4864:20::b49]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1qQuH1-0032sm-35 for linux-arm-kernel@lists.infradead.org; Tue, 01 Aug 2023 18:39:13 +0000 Received: by mail-yb1-xb49.google.com with SMTP id 3f1490d57ef6-c6dd0e46a52so6173590276.2 for ; Tue, 01 Aug 2023 11:39:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20221208; t=1690915150; x=1691519950; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=EAM03TrWnx19tFyGEZeiC8ZPNwQCzRz5upWzC+FfDMU=; b=noMSpccdCmyKnDBXuUhvYDP77FEjg3MllnGtclhY+xLWvPBZh2jbRYNgjgvWRtIkmq bIlPLJtrytU8jyO/19+MHyU16ZJkdBEOLKn3OVOGP4S/M0e2iPwPOadii30LC0/QCrsj /VO11DM3IrSggkwkNF0djIujCQGV06iHUD3if7dqbyigGV5G/qDx9WLr7ljJYc9y3FJy swqLhI1Yy8hNKVWU+LZ9rVKzcOmdhh7FFZgy6dd7d/YRDjmLUEpHSD8g1JfeoOuxjeOF 8N19Ym5DnZm9mMUzRgCN2b9N20p1nkJ+qxF0lS1c1BMZOJZefzm+DCAGue+VVQRDXuG4 TwZg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1690915150; x=1691519950; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=EAM03TrWnx19tFyGEZeiC8ZPNwQCzRz5upWzC+FfDMU=; b=XZihHLHnET8v4R+FvBrELy+WRpv6FtOlQPplVPVhdaG6lUGno17aeurff1aWrGdp4P 0vWCOaE8oD4noZVFhMMWUx9/1+SAkNytIJGRo/wkxBv4c90z67ZKWlBiy5zHTgP5+0/0 cx8ZgzbyHgsICp2elalaeKO/PhW5OpT3VQOWHjJgTQBVCGF3ktERMA1FxCTjXz50powc dJ5T9pGZAbL7gOzRyA0riLsxsJ1IZAeTQpjbYif3gqFuPmT66WnTtP/echjGxVhZqtc1 5lN2udDpPpl+XSUn2EEXscNOpY7V+xNF2X1WFFAXKtiU5ob4I2vgxdacdBc3d9PcIhZC HPFQ== X-Gm-Message-State: ABy/qLbHjyfQ16zAxJmob46in+JE4ePP/PDGAtfe+297oFoXeqawLZC5 B2Fv43AiRpvbA7KhEywuc9qAN+X7ikvU X-Google-Smtp-Source: APBJJlELAdnlXVRI73meTrkv0tFhH71JQ7/kij7cS8tztEz4dJhJ4HmsuRl7WLAvqGssIbMBx5is4LmVBjRt X-Received: from mshavit.ntc.corp.google.com ([2401:fa00:95:20c:a54:d53d:50e4:b5b8]) (user=mshavit job=sendgmr) by 2002:a25:7493:0:b0:d09:17f2:d3b0 with SMTP id p141-20020a257493000000b00d0917f2d3b0mr94958ybc.9.1690915150758; Tue, 01 Aug 2023 11:39:10 -0700 (PDT) Date: Wed, 2 Aug 2023 02:35:21 +0800 In-Reply-To: <20230801183845.4026101-1-mshavit@google.com> Mime-Version: 1.0 References: <20230801183845.4026101-1-mshavit@google.com> X-Mailer: git-send-email 2.41.0.585.gd2178a4bd4-goog Message-ID: <20230802023524.v3.4.I5aa89c849228794a64146cfe86df21fb71629384@changeid> Subject: [PATCH v3 4/8] iommu/arm-smmu-v3: move stall_enabled to the cd table From: Michael Shavit To: iommu@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: robin.murphy@arm.com, will@kernel.org, jean-philippe@linaro.org, jgg@nvidia.com, nicolinc@nvidia.com, Michael Shavit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230801_113911_989513_71356D34 X-CRM114-Status: GOOD ( 18.62 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org This controls whether CD entries will have the stall bit set when writing entries into the table. Signed-off-by: Michael Shavit Reviewed-by: Jason Gunthorpe --- (no changes since v2) Changes in v2: - Use a bitfield instead of a bool for stall_enabled drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 8 ++++---- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 3 ++- 2 files changed, 6 insertions(+), 5 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index fe4b19c3b8dee..c01023404c26c 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -1114,7 +1114,7 @@ int arm_smmu_write_ctx_desc(struct arm_smmu_domain *smmu_domain, int ssid, FIELD_PREP(CTXDESC_CD_0_ASID, cd->asid) | CTXDESC_CD_0_V; - if (smmu_domain->stall_enabled) + if (smmu_domain->cd_table.stall_enabled) val |= CTXDESC_CD_0_S; } @@ -1141,6 +1141,7 @@ static int arm_smmu_alloc_cd_tables(struct arm_smmu_domain *smmu_domain, struct arm_smmu_device *smmu = smmu_domain->smmu; struct arm_smmu_ctx_desc_cfg *cdcfg = &smmu_domain->cd_table; + cdcfg->stall_enabled = master->stall_enabled; cdcfg->max_cds_bits = master->ssid_bits; max_contexts = 1 << cdcfg->max_cds_bits; @@ -2121,8 +2122,6 @@ static int arm_smmu_domain_finalise_s1(struct arm_smmu_domain *smmu_domain, if (ret) goto out_unlock; - smmu_domain->stall_enabled = master->stall_enabled; - ret = arm_smmu_alloc_cd_tables(smmu_domain, master); if (ret) goto out_free_asid; @@ -2461,7 +2460,8 @@ static int arm_smmu_attach_dev(struct iommu_domain *domain, struct device *dev) ret = -EINVAL; goto out_unlock; } else if (smmu_domain->stage == ARM_SMMU_DOMAIN_S1 && - smmu_domain->stall_enabled != master->stall_enabled) { + smmu_domain->cd_table.stall_enabled != + master->stall_enabled) { ret = -EINVAL; goto out_unlock; } diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h index 35a93e8858872..05b1f0ee60808 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -597,6 +597,8 @@ struct arm_smmu_ctx_desc_cfg { unsigned int num_l1_ents; /* log2 of the maximum number of CDs supported by this table */ u8 max_cds_bits; + /* Whether CD entries in this table have the stall bit set. */ + u8 stall_enabled:1; }; struct arm_smmu_s2_cfg { @@ -714,7 +716,6 @@ struct arm_smmu_domain { struct mutex init_mutex; /* Protects smmu pointer */ struct io_pgtable_ops *pgtbl_ops; - bool stall_enabled; atomic_t nr_ats_masters; enum arm_smmu_domain_stage stage;