| Message ID | 20230804072850.89365-13-angelogioacchino.delregno@collabora.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | MediaTek DDP GAMMA - 12-bit LUT support | expand |
Hi, Angelo: On Fri, 2023-08-04 at 09:28 +0200, AngeloGioacchino Del Regno wrote: > Disable relay mode at the end of LUT programming to make sure that > the > processed image goes through in both DISP_GAMMA and DISP_AAL for > gamma > setting. > > Signed-off-by: AngeloGioacchino Del Regno < > angelogioacchino.delregno@collabora.com> > Reviewed-by: Jason-JH.Lin <jason-jh.lin@mediatek.com> > Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com> > --- > drivers/gpu/drm/mediatek/mtk_disp_aal.c | 3 +++ > drivers/gpu/drm/mediatek/mtk_disp_gamma.c | 4 ++++ > 2 files changed, 7 insertions(+) > > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_aal.c > b/drivers/gpu/drm/mediatek/mtk_disp_aal.c > index 21b25470e9b7..992dc1424c91 100644 > --- a/drivers/gpu/drm/mediatek/mtk_disp_aal.c > +++ b/drivers/gpu/drm/mediatek/mtk_disp_aal.c > @@ -122,6 +122,9 @@ void mtk_aal_gamma_set(struct device *dev, struct > drm_crtc_state *state) > writel(word, (aal->regs + DISP_AAL_GAMMA_LUT) + (i * > 4)); > } > > + /* Disable RELAY mode to pass the processed image */ > + cfg_val &= ~AAL_RELAY_MODE; It seems that the relay mode is default turned off. But explicitly setting it is good to me. After adding AAL_RELAY_MODE definition in this patch, Reviewed-by: CK Hu <ck.hu@mediatek.com> > + > writel(cfg_val, aal->regs + DISP_AAL_CFG); > } > > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c > b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c > index 7d2f8042ace0..fbff9f97b737 100644 > --- a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c > +++ b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c > @@ -19,6 +19,7 @@ > #define DISP_GAMMA_EN 0x0000 > #define GAMMA_EN BIT(0) > #define DISP_GAMMA_CFG 0x0020 > +#define GAMMA_RELAY_MODE BIT(0) > #define GAMMA_LUT_EN BIT(1) > #define GAMMA_DITHERING BIT(2) > #define DISP_GAMMA_SIZE 0x0030 > @@ -177,6 +178,9 @@ void mtk_gamma_set(struct device *dev, struct > drm_crtc_state *state) > /* Enable the gamma table */ > cfg_val |= FIELD_PREP(GAMMA_LUT_EN, 1); > > + /* Disable RELAY mode to pass the processed image */ > + cfg_val &= ~GAMMA_RELAY_MODE; > + > writel(cfg_val, gamma->regs + DISP_GAMMA_CFG); > } >
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_aal.c b/drivers/gpu/drm/mediatek/mtk_disp_aal.c index 21b25470e9b7..992dc1424c91 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_aal.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_aal.c @@ -122,6 +122,9 @@ void mtk_aal_gamma_set(struct device *dev, struct drm_crtc_state *state) writel(word, (aal->regs + DISP_AAL_GAMMA_LUT) + (i * 4)); } + /* Disable RELAY mode to pass the processed image */ + cfg_val &= ~AAL_RELAY_MODE; + writel(cfg_val, aal->regs + DISP_AAL_CFG); } diff --git a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c index 7d2f8042ace0..fbff9f97b737 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c @@ -19,6 +19,7 @@ #define DISP_GAMMA_EN 0x0000 #define GAMMA_EN BIT(0) #define DISP_GAMMA_CFG 0x0020 +#define GAMMA_RELAY_MODE BIT(0) #define GAMMA_LUT_EN BIT(1) #define GAMMA_DITHERING BIT(2) #define DISP_GAMMA_SIZE 0x0030 @@ -177,6 +178,9 @@ void mtk_gamma_set(struct device *dev, struct drm_crtc_state *state) /* Enable the gamma table */ cfg_val |= FIELD_PREP(GAMMA_LUT_EN, 1); + /* Disable RELAY mode to pass the processed image */ + cfg_val &= ~GAMMA_RELAY_MODE; + writel(cfg_val, gamma->regs + DISP_GAMMA_CFG); }