From patchwork Fri Aug 4 08:52:16 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: James Clark X-Patchwork-Id: 13341533 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 14900C001DB for ; Fri, 4 Aug 2023 08:53:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=lt/fKmDGfwYXZIYWLS/m4fV74WKmafHbRJup3MlKGws=; b=Cyrixgvz3RERjX FziWO1byYaYymOL8OmFqQo0S7y6EKorDuYA+v7lNW2Rs4NFBb32Y7n6SKs3ysAWpgf0hjOwjPzNYo reFfpuhwrfo9xH8zAL3CoBqL4W+X8P9LEjhikM+RQWsBodMpp5XSDdHgbHuWLQgBFkAbF/07hFyZx /wGgjmKsJ21ZVgDG3uGJpYqJbwKoE5WXjNkgKG/qFC337RwMxcatE/bxLwYbWwVuzhqpdzgWoCjep xz/YKx+dmytsHavDxu/ydGvQbROA+2j8WwCmy3qpXJvL33bwaAQF3APyVmlo8qvQyQ+EbgEyuNxf5 4ToVykHOiLRnqYbaHu6Q==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qRqYA-00BwVy-1z; Fri, 04 Aug 2023 08:52:46 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qRqY7-00BwVP-2z for linux-arm-kernel@lists.infradead.org; Fri, 04 Aug 2023 08:52:45 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id E90921007; Fri, 4 Aug 2023 01:53:24 -0700 (PDT) Received: from e127643.arm.com (unknown [10.57.3.154]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 3C4D23F6C4; Fri, 4 Aug 2023 01:52:39 -0700 (PDT) From: James Clark To: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org Cc: James Clark , Catalin Marinas , Will Deacon , Suzuki K Poulose , Mike Leach , Leo Yan , Alexander Shishkin , Mark Brown , James Morse , Kristina Martsenko , Anshuman Khandual , Rob Herring , Jintack Lim , Joey Gouly , linux-kernel@vger.kernel.org Subject: [PATCH 1/2] arm64/sysreg: Move TRFCR definitions to sysreg Date: Fri, 4 Aug 2023 09:52:16 +0100 Message-Id: <20230804085219.260790-2-james.clark@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230804085219.260790-1-james.clark@arm.com> References: <20230804085219.260790-1-james.clark@arm.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230804_015244_059986_19E3ECE6 X-CRM114-Status: GOOD ( 10.57 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org TRFCR_EL2_CX needs to become TRFCR_ELx_CX to avoid unnecessary duplication and make the SysregFields block re-usable. Signed-off-by: James Clark Reviewed-by: Mark Brown --- arch/arm64/include/asm/sysreg.h | 12 ---------- arch/arm64/tools/sysreg | 22 +++++++++++++++++++ .../coresight/coresight-etm4x-core.c | 2 +- 3 files changed, 23 insertions(+), 13 deletions(-) diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index b481935e9314..fc9a5a09fa04 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -171,8 +171,6 @@ #define SYS_RGSR_EL1 sys_reg(3, 0, 1, 0, 5) #define SYS_GCR_EL1 sys_reg(3, 0, 1, 0, 6) -#define SYS_TRFCR_EL1 sys_reg(3, 0, 1, 2, 1) - #define SYS_TCR_EL1 sys_reg(3, 0, 2, 0, 2) #define SYS_APIAKEYLO_EL1 sys_reg(3, 0, 2, 1, 0) @@ -382,7 +380,6 @@ #define SYS_VTTBR_EL2 sys_reg(3, 4, 2, 1, 0) #define SYS_VTCR_EL2 sys_reg(3, 4, 2, 1, 2) -#define SYS_TRFCR_EL2 sys_reg(3, 4, 1, 2, 1) #define SYS_HDFGRTR_EL2 sys_reg(3, 4, 3, 1, 4) #define SYS_HDFGWTR_EL2 sys_reg(3, 4, 3, 1, 5) #define SYS_HAFGRTR_EL2 sys_reg(3, 4, 3, 1, 6) @@ -640,15 +637,6 @@ /* Safe value for MPIDR_EL1: Bit31:RES1, Bit30:U:0, Bit24:MT:0 */ #define SYS_MPIDR_SAFE_VAL (BIT(31)) -#define TRFCR_ELx_TS_SHIFT 5 -#define TRFCR_ELx_TS_MASK ((0x3UL) << TRFCR_ELx_TS_SHIFT) -#define TRFCR_ELx_TS_VIRTUAL ((0x1UL) << TRFCR_ELx_TS_SHIFT) -#define TRFCR_ELx_TS_GUEST_PHYSICAL ((0x2UL) << TRFCR_ELx_TS_SHIFT) -#define TRFCR_ELx_TS_PHYSICAL ((0x3UL) << TRFCR_ELx_TS_SHIFT) -#define TRFCR_EL2_CX BIT(3) -#define TRFCR_ELx_ExTRE BIT(1) -#define TRFCR_ELx_E0TRE BIT(0) - /* GIC Hypervisor interface registers */ /* ICH_MISR_EL2 bit definitions */ #define ICH_MISR_EOI (1 << 0) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 65866bf819c3..fe1f824977d9 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -2495,3 +2495,25 @@ Field 5 F Field 4 P Field 3:0 Align EndSysreg + +SysregFields TRFCR_ELx +Res0 63:7 +UnsignedEnum 6:5 TS + 0b0001 VIRTUAL + 0b0010 GUEST_PHYSICAL + 0b0011 PHYSICAL +EndEnum +Res0 4 +Field 3 CX +Res0 2 +Field 1 ExTRE +Field 0 E0TRE +EndSysregFields + +Sysreg TRFCR_EL1 3 0 1 2 1 +Fields TRFCR_ELx +EndSysreg + +Sysreg TRFCR_EL2 3 4 1 2 1 +Fields TRFCR_ELx +EndSysreg diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c index 703b6fcbb6a5..257e5c1a4b52 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -1145,7 +1145,7 @@ static void cpu_detect_trace_filtering(struct etmv4_drvdata *drvdata) /* If we are running at EL2, allow tracing the CONTEXTIDR_EL2. */ if (is_kernel_in_hyp_mode()) - trfcr |= TRFCR_EL2_CX; + trfcr |= TRFCR_ELx_CX; drvdata->trfcr = trfcr; }