| Message ID | 20230808072748.374345-1-xu.yang_2@nxp.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [v3,1/2] perf/imx_ddr: speed up overflow frequency of cycle | expand |
> -----Original Message----- > From: Xu Yang <xu.yang_2@nxp.com> > Sent: Tuesday, August 8, 2023 2:28 AM > To: Frank Li <frank.li@nxp.com> > Cc: will@kernel.org; mark.rutland@arm.com; shawnguo@kernel.org; > s.hauer@pengutronix.de; kernel@pengutronix.de; dl-linux-imx <linux- > imx@nxp.com>; linux-arm-kernel@lists.infradead.org > Subject: [PATCH v3 1/2] perf/imx_ddr: speed up overflow frequency of cycle > > For i.MX8MP, we cannot ensure that cycle counter overflow occurs at least > 4 times as often as other events. Due to byte counters will count for any > event configured, it will overflow more often. And if byte counters > overflow that related counters would stop since they share the > COUNTER_CNTL. We can speed up cycle counter overflow frequency by > setting > counter parameter (CP) field of cycle counter. In this way, we can avoid > stop counting byte counters when interrupt didn't come and the byte > counters can be fetched or updated from each cycle counter overflow > interrupt. > > Because we initialize CP filed to shorten counter0 overflow time, the cycle > counter will start couting from a fixed/base value each time. We need to > remove the base from the result too. Therefore, we could get precise result > from cycle counter. > > Signed-off-by: Xu Yang <xu.yang_2@nxp.com> > > --- > Changes in v3: > - modify the comments as suggested from Mark > - use mask to remove bias value > - merge two patches to one > Changes in v2: > - improve if condition > --- > drivers/perf/fsl_imx8_ddr_perf.c | 21 +++++++++++++++++++++ > 1 file changed, 21 insertions(+) > > diff --git a/drivers/perf/fsl_imx8_ddr_perf.c > b/drivers/perf/fsl_imx8_ddr_perf.c > index 5222ba1e79d0..f8a94c051f41 100644 > --- a/drivers/perf/fsl_imx8_ddr_perf.c > +++ b/drivers/perf/fsl_imx8_ddr_perf.c > @@ -28,6 +28,8 @@ > #define CNTL_CLEAR_MASK 0xFFFFFFFD > #define CNTL_OVER_MASK 0xFFFFFFFE > > +#define CNTL_CP_SHIFT 16 > +#define CNTL_CP_MASK (0xFF << CNTL_CP_SHIFT) > #define CNTL_CSV_SHIFT 24 > #define CNTL_CSV_MASK (0xFFU << CNTL_CSV_SHIFT) > > @@ -427,6 +429,17 @@ static void ddr_perf_counter_enable(struct > ddr_pmu *pmu, int config, > writel(0, pmu->base + reg); > val = CNTL_EN | CNTL_CLEAR; > val |= FIELD_PREP(CNTL_CSV_MASK, config); > + > + /* > + * On i.MX8MP we need to bias the cycle counter to overflow > more often. > + * We do this by initializing bits [31:28] of the counter value > via the > + * COUNTER_CTRL Counter Parameter (CP) field. > + */ > + if (pmu->devtype_data->quirks & > DDR_CAP_AXI_ID_FILTER_ENHANCED) { > + if (counter == EVENT_CYCLES_COUNTER) > + val |= FIELD_PREP(CNTL_CP_MASK, 0xf0); Comment said init bits 31: 28, CNTL_CP_MASK is 0xFF << 16. It is bits 24:16. > + } > + > writel(val, pmu->base + reg); > } else { > /* Disable counter */ > @@ -466,6 +479,14 @@ static void ddr_perf_event_update(struct > perf_event *event) > int ret; > > new_raw_count = ddr_perf_read_counter(pmu, counter); > + /* > + * Remove the bias applied in ddr_perf_counter_enable(). > + */ > + if (pmu->devtype_data->quirks & > DDR_CAP_AXI_ID_FILTER_ENHANCED) { > + if (counter == EVENT_CYCLES_COUNTER) > + new_raw_count &= 0x0fffffff; Is it ~ CNTL_CP_MASK? > + } > + > local64_add(new_raw_count, &event->count); > > /* > -- > 2.34.1
> > -----Original Message----- > > From: Xu Yang <xu.yang_2@nxp.com> > > Sent: Tuesday, August 8, 2023 2:28 AM > > To: Frank Li <frank.li@nxp.com> > > Cc: will@kernel.org; mark.rutland@arm.com; shawnguo@kernel.org; > > s.hauer@pengutronix.de; kernel@pengutronix.de; dl-linux-imx <linux- > > imx@nxp.com>; linux-arm-kernel@lists.infradead.org > > Subject: [PATCH v3 1/2] perf/imx_ddr: speed up overflow frequency of cycle > > > > For i.MX8MP, we cannot ensure that cycle counter overflow occurs at least > > 4 times as often as other events. Due to byte counters will count for any > > event configured, it will overflow more often. And if byte counters > > overflow that related counters would stop since they share the > > COUNTER_CNTL. We can speed up cycle counter overflow frequency by > > setting > > counter parameter (CP) field of cycle counter. In this way, we can avoid > > stop counting byte counters when interrupt didn't come and the byte > > counters can be fetched or updated from each cycle counter overflow > > interrupt. > > > > Because we initialize CP filed to shorten counter0 overflow time, the cycle > > counter will start couting from a fixed/base value each time. We need to > > remove the base from the result too. Therefore, we could get precise result > > from cycle counter. > > > > Signed-off-by: Xu Yang <xu.yang_2@nxp.com> > > > > --- > > Changes in v3: > > - modify the comments as suggested from Mark > > - use mask to remove bias value > > - merge two patches to one > > Changes in v2: > > - improve if condition > > --- > > drivers/perf/fsl_imx8_ddr_perf.c | 21 +++++++++++++++++++++ > > 1 file changed, 21 insertions(+) > > > > diff --git a/drivers/perf/fsl_imx8_ddr_perf.c > > b/drivers/perf/fsl_imx8_ddr_perf.c > > index 5222ba1e79d0..f8a94c051f41 100644 > > --- a/drivers/perf/fsl_imx8_ddr_perf.c > > +++ b/drivers/perf/fsl_imx8_ddr_perf.c > > @@ -28,6 +28,8 @@ > > #define CNTL_CLEAR_MASK 0xFFFFFFFD > > #define CNTL_OVER_MASK 0xFFFFFFFE > > > > +#define CNTL_CP_SHIFT 16 > > +#define CNTL_CP_MASK (0xFF << CNTL_CP_SHIFT) > > #define CNTL_CSV_SHIFT 24 > > #define CNTL_CSV_MASK (0xFFU << CNTL_CSV_SHIFT) > > > > @@ -427,6 +429,17 @@ static void ddr_perf_counter_enable(struct > > ddr_pmu *pmu, int config, > > writel(0, pmu->base + reg); > > val = CNTL_EN | CNTL_CLEAR; > > val |= FIELD_PREP(CNTL_CSV_MASK, config); > > + > > + /* > > + * On i.MX8MP we need to bias the cycle counter to overflow > > more often. > > + * We do this by initializing bits [31:28] of the counter value > > via the > > + * COUNTER_CTRL Counter Parameter (CP) field. > > + */ > > + if (pmu->devtype_data->quirks & > > DDR_CAP_AXI_ID_FILTER_ENHANCED) { > > + if (counter == EVENT_CYCLES_COUNTER) > > + val |= FIELD_PREP(CNTL_CP_MASK, 0xf0); > > Comment said init bits 31: 28, CNTL_CP_MASK is 0xFF << 16. It is bits 24:16. Yes. > > > + } > > + > > writel(val, pmu->base + reg); > > } else { > > /* Disable counter */ > > @@ -466,6 +479,14 @@ static void ddr_perf_event_update(struct > > perf_event *event) > > int ret; > > > > new_raw_count = ddr_perf_read_counter(pmu, counter); > > + /* > > + * Remove the bias applied in ddr_perf_counter_enable(). > > + */ > > + if (pmu->devtype_data->quirks & > > DDR_CAP_AXI_ID_FILTER_ENHANCED) { > > + if (counter == EVENT_CYCLES_COUNTER) > > + new_raw_count &= 0x0fffffff; > > Is it ~ CNTL_CP_MASK? Not. ~ CNTL_CP_MASK is 0xFF00FFFF. > > > + } > > + > > local64_add(new_raw_count, &event->count); > > > > /* > > -- > > 2.34.1
diff --git a/drivers/perf/fsl_imx8_ddr_perf.c b/drivers/perf/fsl_imx8_ddr_perf.c index 5222ba1e79d0..f8a94c051f41 100644 --- a/drivers/perf/fsl_imx8_ddr_perf.c +++ b/drivers/perf/fsl_imx8_ddr_perf.c @@ -28,6 +28,8 @@ #define CNTL_CLEAR_MASK 0xFFFFFFFD #define CNTL_OVER_MASK 0xFFFFFFFE +#define CNTL_CP_SHIFT 16 +#define CNTL_CP_MASK (0xFF << CNTL_CP_SHIFT) #define CNTL_CSV_SHIFT 24 #define CNTL_CSV_MASK (0xFFU << CNTL_CSV_SHIFT) @@ -427,6 +429,17 @@ static void ddr_perf_counter_enable(struct ddr_pmu *pmu, int config, writel(0, pmu->base + reg); val = CNTL_EN | CNTL_CLEAR; val |= FIELD_PREP(CNTL_CSV_MASK, config); + + /* + * On i.MX8MP we need to bias the cycle counter to overflow more often. + * We do this by initializing bits [31:28] of the counter value via the + * COUNTER_CTRL Counter Parameter (CP) field. + */ + if (pmu->devtype_data->quirks & DDR_CAP_AXI_ID_FILTER_ENHANCED) { + if (counter == EVENT_CYCLES_COUNTER) + val |= FIELD_PREP(CNTL_CP_MASK, 0xf0); + } + writel(val, pmu->base + reg); } else { /* Disable counter */ @@ -466,6 +479,14 @@ static void ddr_perf_event_update(struct perf_event *event) int ret; new_raw_count = ddr_perf_read_counter(pmu, counter); + /* + * Remove the bias applied in ddr_perf_counter_enable(). + */ + if (pmu->devtype_data->quirks & DDR_CAP_AXI_ID_FILTER_ENHANCED) { + if (counter == EVENT_CYCLES_COUNTER) + new_raw_count &= 0x0fffffff; + } + local64_add(new_raw_count, &event->count); /*
For i.MX8MP, we cannot ensure that cycle counter overflow occurs at least 4 times as often as other events. Due to byte counters will count for any event configured, it will overflow more often. And if byte counters overflow that related counters would stop since they share the COUNTER_CNTL. We can speed up cycle counter overflow frequency by setting counter parameter (CP) field of cycle counter. In this way, we can avoid stop counting byte counters when interrupt didn't come and the byte counters can be fetched or updated from each cycle counter overflow interrupt. Because we initialize CP filed to shorten counter0 overflow time, the cycle counter will start couting from a fixed/base value each time. We need to remove the base from the result too. Therefore, we could get precise result from cycle counter. Signed-off-by: Xu Yang <xu.yang_2@nxp.com> --- Changes in v3: - modify the comments as suggested from Mark - use mask to remove bias value - merge two patches to one Changes in v2: - improve if condition --- drivers/perf/fsl_imx8_ddr_perf.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+)