From patchwork Tue Aug 8 08:27:37 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krzysztof Kozlowski X-Patchwork-Id: 13345840 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B3A41C001B0 for ; Tue, 8 Aug 2023 08:28:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:To:From:Reply-To:Cc:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=TbODhEIgDa0Cr/XBiSeFu98HRqeHJfucpnKKD/BWiu8=; b=oSdbpwyG7/uuXV 9Nxem3pqrjNiuwVX929l3tQ81qY0MG41aVFsDcZORx9g+n1H8cwE8r7WRqqnXdI4ENpyna6exaVQ+ bOyLkYdZJnBo9c4ee2pq5Ld8RHgivz5Nz2m07h2wMcHpBw7GjTYkGjEl7mQGdQP3w8z7dl5VIgwxD WfJDd8MRqNcqhkvLGHMhd7xIqQ0J0IROZdNB5WuyMrMnJ4hhN7sowkb6Y9oq9x4jctEkw//FcEuvR 6H4Eke5s1YcqHeASsWQbUL7WCHkoDLq6KHTG7IK4ld8jXpT4W7lya9ft97BcKGzeayqoMzlh7/Pyp JnG4WLnkcbvswnAc0KSQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qTI4h-00213z-2B; Tue, 08 Aug 2023 08:28:19 +0000 Received: from mail-lf1-x130.google.com ([2a00:1450:4864:20::130]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1qTI4U-0020tS-1I for linux-arm-kernel@lists.infradead.org; Tue, 08 Aug 2023 08:28:08 +0000 Received: by mail-lf1-x130.google.com with SMTP id 2adb3069b0e04-4fe0d5f719dso8857053e87.2 for ; Tue, 08 Aug 2023 01:28:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1691483281; x=1692088081; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=Ga9ShVSfRDMx/t8+Pt2uOUsHlvwZxV8rq0HaCpReBAw=; b=Iqw5vk9Sc93vGHleUAfBwTEYFj/EivCQX+rGupO5Rd39eAH6S3mhv13G53JaAcSzrp gB6dP7e6uMgrdQ2z4ohL/AeRJDWL8EZXuHZUU0YdtsVt72HxNRueu7b7fQYwr/VKXCB6 6m8GLx4zzuQBTM5pR9dOKzdfWUipUND2JMy7zPXVV40itJdh3/g2KnuyMqu9g/Csve3g a+Zi0h0aQhI/vbm3zsqR+uDig+nDhP1XTZGnw14XTx2LYDk6kDJqDEemHA++5m15q0Nj fBv8lvD1lyTly5nbbgejU4VHHEe+78dunUHrtVbCW5+aCx41fjrdDqZ79YrqSsGcDnwJ njiw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1691483281; x=1692088081; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Ga9ShVSfRDMx/t8+Pt2uOUsHlvwZxV8rq0HaCpReBAw=; b=keiRwVlAjypProPZnypR0BCXWifBnZ3nKmqf1KB3G26mx8QEsnQErQzlST+/aNJYVZ 3YJQOoMHuDUfsBPsbNVM01yVzml7hy+Xot7+ZVzTGzYdBIboIVQ7mXxKAQbZZmiREcuf SweGsjdAnjqyJFhA9qmSDz1QLVaDUlXk5oWTa9et46fX6HgQjnxRa/ePHeaXd3vxdOB/ UNvwHbrRNowrAKPJ+2htfd2o3AOoljyM+J6UFFF2Jdwissf1hTUn6xBOLqYLr7MIDnGY qybT66s9uMO5F6ve8erySsBZo+art1wbxVfS0R21SqbQPDAFzu8CdyQyjIE8lR/bc+Wy Cdzw== X-Gm-Message-State: AOJu0YynpwzWN1+ropRd0dCfsGxQ8p3U8aftkdKegZ0jxuLnqd5mWinK 6i17feuYopPfvRExdqgNAM5ufg== X-Google-Smtp-Source: AGHT+IGoYdIOrAk32Xpjqu5lGI0d77DrpYLqBhLO0RsGUXKf+OwfLW2ec1eVNHj/KnbQGKFgnC4TGw== X-Received: by 2002:a05:6512:3d8e:b0:4f8:7568:e948 with SMTP id k14-20020a0565123d8e00b004f87568e948mr9356536lfv.51.1691483281731; Tue, 08 Aug 2023 01:28:01 -0700 (PDT) Received: from krzk-bin.. ([178.197.222.113]) by smtp.gmail.com with ESMTPSA id s18-20020adfeb12000000b0031779a6b451sm12861246wrn.83.2023.08.08.01.28.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Aug 2023 01:28:01 -0700 (PDT) From: Krzysztof Kozlowski To: Krzysztof Kozlowski , Sylwester Nawrocki , Tomasz Figa , Chanwoo Choi , Alim Akhtar , Michael Turquette , Stephen Boyd , Rob Herring , Conor Dooley , linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH 10/11] clk: samsung: exynoautov9: do not define number of clocks in bindings Date: Tue, 8 Aug 2023 10:27:37 +0200 Message-Id: <20230808082738.122804-11-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230808082738.122804-1-krzysztof.kozlowski@linaro.org> References: <20230808082738.122804-1-krzysztof.kozlowski@linaro.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230808_012806_460952_891C71FD X-CRM114-Status: GOOD ( 14.44 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Number of clocks supported by Linux drivers might vary - sometimes we add new clocks, not exposed previously. Therefore this number of clocks should not be in the bindings, because otherwise we should not change it. Define number of clocks per each clock controller inside the driver directly. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Alim Akhtar --- drivers/clk/samsung/clk-exynosautov9.c | 29 ++++++++++++++++++-------- 1 file changed, 20 insertions(+), 9 deletions(-) diff --git a/drivers/clk/samsung/clk-exynosautov9.c b/drivers/clk/samsung/clk-exynosautov9.c index ddef546be545..e9c06eb93e66 100644 --- a/drivers/clk/samsung/clk-exynosautov9.c +++ b/drivers/clk/samsung/clk-exynosautov9.c @@ -16,6 +16,17 @@ #include "clk.h" #include "clk-exynos-arm64.h" +/* NOTE: Must be equal to the last clock ID increased by one */ +#define CLKS_NR_TOP (GOUT_CLKCMU_PERIS_BUS + 1) +#define CLKS_NR_BUSMC (CLK_GOUT_BUSMC_SPDMA_PCLK + 1) +#define CLKS_NR_CORE (CLK_GOUT_CORE_CMU_CORE_PCLK + 1) +#define CLKS_NR_FSYS0 (CLK_GOUT_FSYS0_PCIE_GEN3B_4L_CLK + 1) +#define CLKS_NR_FSYS1 (CLK_GOUT_FSYS1_USB30_1_ACLK + 1) +#define CLKS_NR_FSYS2 (CLK_GOUT_FSYS2_UFS_EMBD1_UNIPRO + 1) +#define CLKS_NR_PERIC0 (CLK_GOUT_PERIC0_PCLK_11 + 1) +#define CLKS_NR_PERIC1 (CLK_GOUT_PERIC1_PCLK_11 + 1) +#define CLKS_NR_PERIS (CLK_GOUT_WDT_CLUSTER1 + 1) + /* ---- CMU_TOP ------------------------------------------------------------ */ /* Register Offset definitions for CMU_TOP (0x1b240000) */ @@ -941,7 +952,7 @@ static const struct samsung_cmu_info top_cmu_info __initconst = { .nr_fixed_factor_clks = ARRAY_SIZE(top_fixed_factor_clks), .gate_clks = top_gate_clks, .nr_gate_clks = ARRAY_SIZE(top_gate_clks), - .nr_clk_ids = TOP_NR_CLK, + .nr_clk_ids = CLKS_NR_TOP, .clk_regs = top_clk_regs, .nr_clk_regs = ARRAY_SIZE(top_clk_regs), }; @@ -1001,7 +1012,7 @@ static const struct samsung_cmu_info busmc_cmu_info __initconst = { .nr_div_clks = ARRAY_SIZE(busmc_div_clks), .gate_clks = busmc_gate_clks, .nr_gate_clks = ARRAY_SIZE(busmc_gate_clks), - .nr_clk_ids = BUSMC_NR_CLK, + .nr_clk_ids = CLKS_NR_BUSMC, .clk_regs = busmc_clk_regs, .nr_clk_regs = ARRAY_SIZE(busmc_clk_regs), .clk_name = "dout_clkcmu_busmc_bus", @@ -1059,7 +1070,7 @@ static const struct samsung_cmu_info core_cmu_info __initconst = { .nr_div_clks = ARRAY_SIZE(core_div_clks), .gate_clks = core_gate_clks, .nr_gate_clks = ARRAY_SIZE(core_gate_clks), - .nr_clk_ids = CORE_NR_CLK, + .nr_clk_ids = CLKS_NR_CORE, .clk_regs = core_clk_regs, .nr_clk_regs = ARRAY_SIZE(core_clk_regs), .clk_name = "dout_clkcmu_core_bus", @@ -1299,7 +1310,7 @@ static const struct samsung_cmu_info fsys0_cmu_info __initconst = { .nr_mux_clks = ARRAY_SIZE(fsys0_mux_clks), .gate_clks = fsys0_gate_clks, .nr_gate_clks = ARRAY_SIZE(fsys0_gate_clks), - .nr_clk_ids = FSYS0_NR_CLK, + .nr_clk_ids = CLKS_NR_FSYS0, .clk_regs = fsys0_clk_regs, .nr_clk_regs = ARRAY_SIZE(fsys0_clk_regs), .clk_name = "dout_clkcmu_fsys0_bus", @@ -1426,7 +1437,7 @@ static const struct samsung_cmu_info fsys1_cmu_info __initconst = { .nr_div_clks = ARRAY_SIZE(fsys1_div_clks), .gate_clks = fsys1_gate_clks, .nr_gate_clks = ARRAY_SIZE(fsys1_gate_clks), - .nr_clk_ids = FSYS1_NR_CLK, + .nr_clk_ids = CLKS_NR_FSYS1, .clk_regs = fsys1_clk_regs, .nr_clk_regs = ARRAY_SIZE(fsys1_clk_regs), .clk_name = "dout_clkcmu_fsys1_bus", @@ -1493,7 +1504,7 @@ static const struct samsung_cmu_info fsys2_cmu_info __initconst = { .nr_mux_clks = ARRAY_SIZE(fsys2_mux_clks), .gate_clks = fsys2_gate_clks, .nr_gate_clks = ARRAY_SIZE(fsys2_gate_clks), - .nr_clk_ids = FSYS2_NR_CLK, + .nr_clk_ids = CLKS_NR_FSYS2, .clk_regs = fsys2_clk_regs, .nr_clk_regs = ARRAY_SIZE(fsys2_clk_regs), .clk_name = "dout_clkcmu_fsys2_bus", @@ -1748,7 +1759,7 @@ static const struct samsung_cmu_info peric0_cmu_info __initconst = { .nr_div_clks = ARRAY_SIZE(peric0_div_clks), .gate_clks = peric0_gate_clks, .nr_gate_clks = ARRAY_SIZE(peric0_gate_clks), - .nr_clk_ids = PERIC0_NR_CLK, + .nr_clk_ids = CLKS_NR_PERIC0, .clk_regs = peric0_clk_regs, .nr_clk_regs = ARRAY_SIZE(peric0_clk_regs), .clk_name = "dout_clkcmu_peric0_bus", @@ -2003,7 +2014,7 @@ static const struct samsung_cmu_info peric1_cmu_info __initconst = { .nr_div_clks = ARRAY_SIZE(peric1_div_clks), .gate_clks = peric1_gate_clks, .nr_gate_clks = ARRAY_SIZE(peric1_gate_clks), - .nr_clk_ids = PERIC1_NR_CLK, + .nr_clk_ids = CLKS_NR_PERIC1, .clk_regs = peric1_clk_regs, .nr_clk_regs = ARRAY_SIZE(peric1_clk_regs), .clk_name = "dout_clkcmu_peric1_bus", @@ -2050,7 +2061,7 @@ static const struct samsung_cmu_info peris_cmu_info __initconst = { .nr_mux_clks = ARRAY_SIZE(peris_mux_clks), .gate_clks = peris_gate_clks, .nr_gate_clks = ARRAY_SIZE(peris_gate_clks), - .nr_clk_ids = PERIS_NR_CLK, + .nr_clk_ids = CLKS_NR_PERIS, .clk_regs = peris_clk_regs, .nr_clk_regs = ARRAY_SIZE(peris_clk_regs), .clk_name = "dout_clkcmu_peris_bus",