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Tue, 8 Aug 2023 05:38:06 -0500 From: Thippeswamy Havalige To: , , , , , CC: , , , , "Thippeswamy Havalige" Subject: [PATCH v2 2/2] PCI: xilinx-nwl: Increase ECAM size to accommodate 256 buses. Date: Tue, 8 Aug 2023 16:07:33 +0530 Message-ID: <20230808103733.93707-4-thippeswamy.havalige@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230808103733.93707-1-thippeswamy.havalige@amd.com> References: <20230808103733.93707-1-thippeswamy.havalige@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF0002529E:EE_|DM6PR12MB5006:EE_ X-MS-Office365-Filtering-Correlation-Id: c71c7a90-78d0-4fa4-f44c-08db97fb8f7d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: C1HcHwRi1P5Ds8zHaIv5JNchDbtsOF2qGm+P0v5Ag453fjbrKCDW/6gjWX5ljVG7EsRJIRmtjkuNlfhruNnguU9MEeHIkx++/DbNg8ErlwY7QOOkTrRl3TJq/KZ6MFZjmi1GYoOGQl1wiSA1MTsojdAh/moy83ER/f4Ea77h4Jje8KncIzbzqca/h+uzpg3eSpKWkYimlTLoAM/cs4oiE+A6D+JMqE79P7JRbdGbEALiAmJ8QoN2iebeCmkJ/DEjq37T5BKjlKGHozGFHzLJzgMpjCOBrP8j3frMTI/OUXn6GuCa9W5WWln06T2WpwU3i0Rf7Dla3KaZVJZLXhymuVjnS8cig8OHIiKjtL+zt57p7vhaLDJdegCF7nsQea2fvQ7QzcRlH3pYqHVl7nW3oli0soJjdNAvC6ry9q/yTE2AiI5Es5DTg3/thBfWWRLQIrXJZfxrU35cxayIRr+J18fEy3DFnMoog7dyfY25mQyPApNUuSR3WT5jnrhX2+oZrxAUY56vn77kTYx5y+y7F2QJJ9Bnefz9GqHR8JtqBT0iich2og5wqI1gfkPOfyBY3lUvmKe4nHjId/26ZUHYDM5iESQYiqW9ZrRJYWismN6GQyZ5nMt9u+19PSjtAucqEhmMoV5a/VmW8hnxkekC97eCR3UvZEGaWOuipWV7xqaDObkvM2GGGr0UxD9gW6yCTGRvDpQC9rs7fI3bD+8XwJz1V/+LzVY2Vf6IsiClieNhpbCvezM7w0YCpKoZQB8D2m8EjY6NwrWwJoIS+PxHJg== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230028)(4636009)(396003)(136003)(39860400002)(376002)(346002)(82310400008)(1800799003)(186006)(451199021)(46966006)(36840700001)(40470700004)(2616005)(26005)(1076003)(36756003)(336012)(6666004)(81166007)(478600001)(356005)(82740400003)(110136005)(54906003)(70586007)(70206006)(4326008)(41300700001)(426003)(316002)(8676002)(8936002)(5660300002)(44832011)(40460700003)(2906002)(36860700001)(83380400001)(47076005)(86362001)(40480700001)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Aug 2023 10:38:10.2414 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c71c7a90-78d0-4fa4-f44c-08db97fb8f7d X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF0002529E.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB5006 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230808_033817_432505_544781C8 X-CRM114-Status: GOOD ( 12.25 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Our controller is expecting ECAM size to be programmed by software. By programming "NWL_ECAM_VALUE_DEFAULT 12" controller can access up to 16MB ECAM region which is used to detect 16 buses, so by updating "NWL_ECAM_VALUE_DEFAULT" to 16 so that controller can access up to 256MB ECAM region to detect 256 buses. Signed-off-by: Thippeswamy Havalige Signed-off-by: Bharat Kumar Gogada --- changes in v2: - Update this changes in a seperate patch. --- drivers/pci/controller/pcie-xilinx-nwl.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pci/controller/pcie-xilinx-nwl.c b/drivers/pci/controller/pcie-xilinx-nwl.c index a73554e..b515019 100644 --- a/drivers/pci/controller/pcie-xilinx-nwl.c +++ b/drivers/pci/controller/pcie-xilinx-nwl.c @@ -126,7 +126,7 @@ #define E_ECAM_CR_ENABLE BIT(0) #define E_ECAM_SIZE_LOC GENMASK(20, 16) #define E_ECAM_SIZE_SHIFT 16 -#define NWL_ECAM_VALUE_DEFAULT 12 +#define NWL_ECAM_VALUE_DEFAULT 16 #define CFG_DMA_REG_BAR GENMASK(2, 0) #define CFG_PCIE_CACHE GENMASK(7, 0)