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Mon, 14 Aug 2023 12:14:52 -0500 From: Thippeswamy Havalige To: , , , , , , CC: , , , , "Thippeswamy Havalige" Subject: [PATCH v4 3/3] PCI: xilinx-nwl: Increase ECAM size to accommodate 256 buses Date: Mon, 14 Aug 2023 22:44:06 +0530 Message-ID: <20230814171406.214932-5-thippeswamy.havalige@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230814171406.214932-1-thippeswamy.havalige@amd.com> References: <20230814171406.214932-1-thippeswamy.havalige@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000E9D1:EE_|SN7PR12MB7788:EE_ X-MS-Office365-Filtering-Correlation-Id: d8e04580-292b-4f5d-79b9-08db9cea06d4 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 75arK9BF/8KmzYhJG4MML7Spf6zR6EaaGST/pvEtKv7p5mJZUyRbU44xHuLRWt+C3VwBx5gL3dyCbRIuY1G8IJlN2fT+gIaFZ7m0bSw6b+SYEUhVkKCn0LLJaPx12F+RKzuEC6R8HfnQiMmxhIK2EmALW98LKjevcDmpHq+LGAzYyDsvJHKNgcB3/25vK5EoS8vSLCYDpG/27/ca5BGYDKoCjl925mMFPh4KRpaEkvJVD1NfZfR9NQtCYoDM5KK+lnbNZrvLE7wxQSoXls04DAOAPhfiUvDZqS4xE672jYls5OMgLcL/RgI6bF9r6ZebKCMye26DYPIK6F19ZRZ+7GnO48yFlDn48wKnsuhWwuFg/wmBhz+VNWJ/GD7wwA8e+EF9wslxTg9ciphJGbZ3ty5k+wmJ/lWrD4854V53gvH4Cpksolg89gWBno0lMuzWZnjPiTNezEdkrqUH4U08KOcyLUovz50UOIvQNg7NtznuI6cfHxSJn05zpQEI9qtblW4CeR4nNbIRvm7GIHRktKDmiNntjDSl8VApMDYP4Zm/CP8mAWlJWLwWB0dZbT3Az/2YAZrfPcJbCkdypiHRv0nULtCYLa4rrSo9ene6f4RzF6J+0hClmBwwSUTcmpk9OEEyMvhllUXwLms+HLdD22kcm2fbDh5Al7KDnFLcLte/NYUQ0TOjqJ5+Aqzx3n6x3Dv2umwQqPEVto2nyEPiSlu1qTzqWDPSUv4WGkzPd7BThsSS9oTrnnI/rUDe1J3Q9jrMC0ofPU5lC/rEWBHv0A== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB03.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230028)(4636009)(376002)(396003)(136003)(39860400002)(346002)(186006)(1800799006)(82310400008)(451199021)(46966006)(40470700004)(36840700001)(83380400001)(36756003)(426003)(336012)(47076005)(36860700001)(86362001)(40480700001)(41300700001)(478600001)(356005)(81166007)(54906003)(70586007)(70206006)(316002)(8676002)(5660300002)(4326008)(44832011)(82740400003)(8936002)(110136005)(40460700003)(2616005)(1076003)(26005)(2906002)(6666004)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Aug 2023 17:15:15.2831 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d8e04580-292b-4f5d-79b9-08db9cea06d4 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9D1.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB7788 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230814_101521_314320_F6E414C4 X-CRM114-Status: GOOD ( 13.16 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Our controller is expecting ECAM size to be programmed by software. By programming "NWL_ECAM_VALUE_DEFAULT 12" controller can access up to 16MB ECAM region which is used to detect 16 buses, so by updating "NWL_ECAM_VALUE_DEFAULT" to 16 so that controller can access up to 256MB ECAM region to detect 256 buses. Nothing will break, when having a DT with the smaller ECAM size and boot a kernel that includes this change,but the kernel will only be able to use 16 buses. Signed-off-by: Thippeswamy Havalige --- Changes in v4: Move modified ECAM max size macro into a seperate patch. drivers/pci/controller/pcie-xilinx-nwl.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pci/controller/pcie-xilinx-nwl.c b/drivers/pci/controller/pcie-xilinx-nwl.c index 8fe0e8a325b0..e307aceba5c9 100644 --- a/drivers/pci/controller/pcie-xilinx-nwl.c +++ b/drivers/pci/controller/pcie-xilinx-nwl.c @@ -126,7 +126,7 @@ #define E_ECAM_CR_ENABLE BIT(0) #define E_ECAM_SIZE_LOC GENMASK(20, 16) #define E_ECAM_SIZE_SHIFT 16 -#define NWL_ECAM_MAX_SIZE 12 +#define NWL_ECAM_MAX_SIZE 16 #define CFG_DMA_REG_BAR GENMASK(2, 0) #define CFG_PCIE_CACHE GENMASK(7, 0)