| Message ID | 20230815231117.15169-1-aford173@gmail.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [V2,1/2] arm64: dts: imx8mp: Fix SDMA2/3 clocks | expand |
Hi Adam, On Tue, Aug 15, 2023 at 8:11 PM Adam Ford <aford173@gmail.com> wrote: > > A previous patch to remove the Audio clocks from the main clock node Nit: Instead of referring to "A previous patch", it would be clearer to explicitly refer to the actual commit. > was intended to force people to setup the audio PLL clocks per board > instead of having a common set of rates since not all boards may use > the various audio PLL clocks for audio devices. > > Unfortunately, with this parenting removed, the SDMA2 and SDMA3 > clocks were slowed to 24MHz because the SDMA2/3 clocks are controlled > via the audio_blk_ctrl which is clocked from IMX8MP_CLK_AUDIO_ROOT, > and that clock is enabled by pgc_audio. > > Per the TRM, "The SDMA2/3 target frequency is 400MHz IPG and 400MHz > AHB, always 1:1 mode, to make sure there is enough throughput for all > the audio use cases." > > Instead of cluttering the clock node, place the clock rate and parent > information into the pgc_audio node. > > With the parenting and clock rates restored for IMX8MP_CLK_AUDIO_AHB, > and IMX8MP_CLK_AUDIO_AXI_SRC, it appears the SDMA2 and SDMA3 run at > 400MHz again. > > Fixes: 16c984524862 ("arm64: dts: imx8mp: don't initialize audio clocks from CCM node") > Signed-off-by: Adam Ford <aford173@gmail.com> > Reviewed-by: Lucas Stach <l.stach@pengutronix.de> Reviewed-by: Fabio Estevam <festevam@gmail.com>
On Tue, Aug 15, 2023 at 8:58 PM Fabio Estevam <festevam@gmail.com> wrote: > > Hi Adam, > > On Tue, Aug 15, 2023 at 8:11 PM Adam Ford <aford173@gmail.com> wrote: > > > > A previous patch to remove the Audio clocks from the main clock node > > Nit: Instead of referring to "A previous patch", it would be clearer > to explicitly > refer to the actual commit. I tried to do that with the fixes tag below. Do you want me to re-submit the patches with this changed? I was hoping to avoid referencing the same patch and hash twice in the same commit message. adam > > > was intended to force people to setup the audio PLL clocks per board > > instead of having a common set of rates since not all boards may use > > the various audio PLL clocks for audio devices. > > > > Unfortunately, with this parenting removed, the SDMA2 and SDMA3 > > clocks were slowed to 24MHz because the SDMA2/3 clocks are controlled > > via the audio_blk_ctrl which is clocked from IMX8MP_CLK_AUDIO_ROOT, > > and that clock is enabled by pgc_audio. > > > > Per the TRM, "The SDMA2/3 target frequency is 400MHz IPG and 400MHz > > AHB, always 1:1 mode, to make sure there is enough throughput for all > > the audio use cases." > > > > Instead of cluttering the clock node, place the clock rate and parent > > information into the pgc_audio node. > > > > With the parenting and clock rates restored for IMX8MP_CLK_AUDIO_AHB, > > and IMX8MP_CLK_AUDIO_AXI_SRC, it appears the SDMA2 and SDMA3 run at > > 400MHz again. > > > > Fixes: 16c984524862 ("arm64: dts: imx8mp: don't initialize audio clocks from CCM node") > > Signed-off-by: Adam Ford <aford173@gmail.com> > > Reviewed-by: Lucas Stach <l.stach@pengutronix.de> > > Reviewed-by: Fabio Estevam <festevam@gmail.com>
Hi Adam, On Wed, Aug 16, 2023 at 12:34 AM Adam Ford <aford173@gmail.com> wrote: > I tried to do that with the fixes tag below. Do you want me to > re-submit the patches with this changed? I was hoping to avoid > referencing the same patch and hash twice in the same commit message. IMHO there is no problem at all by referencing the same commit hash twice. In fact, it makes it clearer as to what exactly you are referencing. Please re-submit it, thanks.
diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index 6f2f50e1639c..83d907294fbc 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -790,6 +790,12 @@ pgc_audio: power-domain@5 { reg = <IMX8MP_POWER_DOMAIN_AUDIOMIX>; clocks = <&clk IMX8MP_CLK_AUDIO_ROOT>, <&clk IMX8MP_CLK_AUDIO_AXI>; + assigned-clocks = <&clk IMX8MP_CLK_AUDIO_AHB>, + <&clk IMX8MP_CLK_AUDIO_AXI_SRC>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, + <&clk IMX8MP_SYS_PLL1_800M>; + assigned-clock-rates = <400000000>, + <600000000>; }; pgc_gpu2d: power-domain@6 {
A previous patch to remove the Audio clocks from the main clock node was intended to force people to setup the audio PLL clocks per board instead of having a common set of rates since not all boards may use the various audio PLL clocks for audio devices. Unfortunately, with this parenting removed, the SDMA2 and SDMA3 clocks were slowed to 24MHz because the SDMA2/3 clocks are controlled via the audio_blk_ctrl which is clocked from IMX8MP_CLK_AUDIO_ROOT, and that clock is enabled by pgc_audio. Per the TRM, "The SDMA2/3 target frequency is 400MHz IPG and 400MHz AHB, always 1:1 mode, to make sure there is enough throughput for all the audio use cases." Instead of cluttering the clock node, place the clock rate and parent information into the pgc_audio node. With the parenting and clock rates restored for IMX8MP_CLK_AUDIO_AHB, and IMX8MP_CLK_AUDIO_AXI_SRC, it appears the SDMA2 and SDMA3 run at 400MHz again. Fixes: 16c984524862 ("arm64: dts: imx8mp: don't initialize audio clocks from CCM node") Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Lucas Stach <l.stach@pengutronix.de> --- V2: Slow AUDIO_AXI to 600MHz for nominal drive. Individual boards can increase this to 800MHz if they have the proper voltage configured.