From patchwork Thu Aug 17 18:16:25 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Shavit X-Patchwork-Id: 13356866 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0458EC3DA58 for ; Thu, 17 Aug 2023 18:22:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:From:Subject:Message-ID: References:Mime-Version:In-Reply-To:Date:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=Vbpvxs1cvKNcPtlwChUcTj1tPZOyI9cMsZsILdnKJk4=; b=acs18M+BVDftn5RNOWI+A+YOLt w8DhC4prMCmbwUjbhCtF1PTKAM+HSKdbAyjK3j+eHmMKVpBjDbwuCwhVYwez/GGfT95fl0A4xp22S GtAipeRTUiv5RGZWf3QlmULne/iDnRyr6DPCDOdramR/JW38BUka8rP3arm486ISdSciNAf9Q6RFR YwkPgwdAil9JHNS/VLllsZ/UcWjihX3I4r6CP68OPNHI/mrUIsWcyAA0tnPUZautfqVZXMCQl4ZXr HF6lDgmyh6vgb9NzXXxqSUOC6aLa5OqYvgktsDPZgo4T1EU6T5+Cv4ejyjPrbvt2ylQd3A5f9+1c/ dOme6sXA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qWhcm-006xSi-1A; Thu, 17 Aug 2023 18:21:36 +0000 Received: from mail-yw1-x114a.google.com ([2607:f8b0:4864:20::114a]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1qWhcZ-006xMa-2d for linux-arm-kernel@lists.infradead.org; Thu, 17 Aug 2023 18:21:25 +0000 Received: by mail-yw1-x114a.google.com with SMTP id 00721157ae682-589a4c6ab34so1184067b3.2 for ; Thu, 17 Aug 2023 11:21:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20221208; t=1692296482; x=1692901282; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=qDt4n1J4/1KupnwBe0I86Sz4ed5LQZ4WNLzvIfe1gZo=; b=TLU1cW+m7veBjvJCVt22MqfUzkVutvDZBMei+cpFgVTvlomXcC6SrvXybk0I8PFDeK J0s4B4BR5MhAx0GQUGPudOjwNxpTYqKRURJUtf+mjLa1UTz+eSTq5lK1zljK/NuuwfkH e5QmOA/bMgXZxTiVSikkw8IGuNL98jt8KCSBtwhvphYMhgo67S0AwI7lM6qb1NDIttpc waqux5KVRo2vm8pKtTECcBtr/GWET+XVZkWy0S+r14MK70nTma6HA4DciTZqYrnoxWzr KiXBqrTLTZm0KSp+x2hKqZtH7Lu3IXkqXxzb2JWh1+ZvZN6HHv4TakrZO3y6rzRNyK7u kK+w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1692296482; x=1692901282; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=qDt4n1J4/1KupnwBe0I86Sz4ed5LQZ4WNLzvIfe1gZo=; b=TlEvZvKfSZ1ISgajMeIF2SVI3gqHbNRI1/QCH7DLUzWLZf9RQOdv33rNG665aoCUjc VJjLO2p+0BqGYrU+Lxeg7CjM4jotvO3BhUrFMXTTL5I0BxZ3WED2yBnb575mlN4Gjs0Q qav14hJYAdxFqd5v9ikMcf3Zbtt3yIvOYgPW6QK1cJfZvtTiWhcrRCICscr5HVgb+ETV 2HY4MeTVcKU9qbMucCoZGronA1Zkc/6XPgJ7QVYj3Y4eBnAXHFipfxceD1f32Bp9t2QF 8Jq/prUmmSeXeJ6UCXuAkx9lUS/rKI390rZK8GaGCnwqpk0QrYwfU/F4jMwd17fvQb9u 8szw== X-Gm-Message-State: AOJu0YyYT8XOy7El31jdEzkN7Gp5RoAohVuWWjNwkOLDRxJEu0LeslVK ZZF3pQpUkZNhxNC9vHQQmmxUS6qWUnWE X-Google-Smtp-Source: AGHT+IH5Zwh7r7Rz5gFgHqHiQdREEibNwM2GiX0YHx6D9zht+8wPq+Qu2t6iFL5s2PieMW+BQhbjjnaNen5u X-Received: from mshavit.ntc.corp.google.com ([2401:fa00:95:20c:4a77:fd20:7069:bdf9]) (user=mshavit job=sendgmr) by 2002:a81:431e:0:b0:573:8316:8d04 with SMTP id q30-20020a81431e000000b0057383168d04mr2703ywa.4.1692296482399; Thu, 17 Aug 2023 11:21:22 -0700 (PDT) Date: Fri, 18 Aug 2023 02:16:25 +0800 In-Reply-To: <20230817182055.1770180-1-mshavit@google.com> Mime-Version: 1.0 References: <20230817182055.1770180-1-mshavit@google.com> X-Mailer: git-send-email 2.42.0.rc1.204.g551eb34607-goog Message-ID: <20230818021629.RFC.v1.3.I326c62dc062aed8d901d319aa665dbe983c7904c@changeid> Subject: [RFC PATCH v1 3/8] iommu/arm-smmu-v3-sva: Allocate new ASID from installed_smmus From: Michael Shavit To: iommu@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: will@kernel.org, jgg@nvidia.com, nicolinc@nvidia.com, tina.zhang@intel.com, jean-philippe@linaro.org, robin.murphy@arm.com, Michael Shavit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230817_112123_869635_50E7B3D8 X-CRM114-Status: GOOD ( 12.62 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Pick an ASID that is within the supported range of all SMMUs that the domain is installed to. Signed-off-by: Michael Shavit --- .../iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c | 23 +++++++++++++++---- 1 file changed, 19 insertions(+), 4 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c index 58def59c36004..ab941e394cae5 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c @@ -82,6 +82,20 @@ static int arm_smmu_write_ctx_desc_devices(struct arm_smmu_domain *smmu_domain, return ret; } +static u32 arm_smmu_domain_max_asid_bits(struct arm_smmu_domain *smmu_domain) +{ + struct arm_smmu_installed_smmu *installed_smmu; + unsigned long flags; + u32 asid_bits = 16; + + spin_lock_irqsave(&smmu_domain->installed_smmus_lock, flags); + list_for_each_entry(installed_smmu, &smmu_domain->installed_smmus, + list) + asid_bits = min(asid_bits, installed_smmu->smmu->asid_bits); + spin_unlock_irqrestore(&smmu_domain->installed_smmus_lock, flags); + return asid_bits; +} + /* * Check if the CPU ASID is available on the SMMU side. If a private context * descriptor is using it, try to replace it. @@ -92,7 +106,6 @@ arm_smmu_share_asid(struct mm_struct *mm, u16 asid) int ret; u32 new_asid; struct arm_smmu_ctx_desc *cd; - struct arm_smmu_device *smmu; struct arm_smmu_domain *smmu_domain; cd = xa_load(&arm_smmu_asid_xa, asid); @@ -108,10 +121,12 @@ arm_smmu_share_asid(struct mm_struct *mm, u16 asid) } smmu_domain = container_of(cd, struct arm_smmu_domain, cd); - smmu = smmu_domain->smmu; - ret = xa_alloc(&arm_smmu_asid_xa, &new_asid, cd, - XA_LIMIT(1, (1 << smmu->asid_bits) - 1), GFP_KERNEL); + ret = xa_alloc( + &arm_smmu_asid_xa, &new_asid, cd, + XA_LIMIT(1, + (1 << arm_smmu_domain_max_asid_bits(smmu_domain)) - 1), + GFP_KERNEL); if (ret) return ERR_PTR(-ENOSPC); /*